Topic
Massively parallel processor array
About: Massively parallel processor array is a research topic. Over the lifetime, 54 publications have been published within this topic receiving 620 citations.
Papers published on a yearly basis
Papers
23 Apr 2007
TL;DR: A new platform for reconfigurable computing has an object-based programming model, with architecture, silicon and tools designed to faithfully realize this model, aimed at application developers using software languages and methodologies.
Abstract: A new platform for reconfigurable computing has an object-based programming model, with architecture, silicon and tools designed to faithfully realize this model. The platform is aimed at application developers using software languages and methodologies. Its objectives are massive performance, long-term scalability, and easy development. In our structural object programming model, objects are strictly encapsulated software programs running concurrently on an asynchronous array of processors and memories. They exchange data and control through a structure of self-synchronizing asynchronous channels. Objects are combined hierarchically to create new objects, connected through the common channel interface. The first chip is a 130nm ASIC with 360 32-bit processors, 360 1KB RAM banks with access engines, and a configurable word-wide channel interconnect. Applications written in Java and block diagrams compile in one minute. Sub-millisecond runtime reconfiguration is inherent.
102 citations
TL;DR: This work has developed a scalable MPPA chip architecture that delivers tera-ops performance with very good energy efficiency in an ordinary 130-nm ASIC, based on the structural object programming model.
Abstract: Programming MPPAs for complex real-time embedded applications is difficult with conventional multiprogramming models, which usually treat communication and synchronization separately. Based on a programming model for massively parallel embedded computing that is reasonable and productive for software developers, we developed a scalable MPPA chip architecture that delivers tera-ops performance with very good energy efficiency in an ordinary 130-nm ASIC. This MPPA's architecture is based on the structural object programming model, which composes strictly encapsulated processing and memory objects in a structure of self-synchronizing channels. Small RISC CPUs and memories execute the objects.
75 citations
Patent•
17 Oct 1994
TL;DR: A massively parallel data processing system consisting of an array of closely spaced cells where each cell has direct output means as well as means for processing, memory and input was proposed in this article.
Abstract: A massively parallel data processing system consisting of an array of closely spaced cells where each cell has direct output means as well as means for processing, memory and input. The data processing system according to the present invention overcomes the von Neumann bottleneck of uniprocessor architectures, the I/O and memory bottlenecks that plague parallel processors, and the input bandwidth bottleneck of high-resolution displays.
51 citations
TL;DR: A real-time hyperspectral SVM classifier whose processing time linearly grows with the number of pixels composing the scene has been implemented, where only 3 µs is required to process each pixel within the captured scene independently from the spatial resolution of the image.
40 citations
31 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2019 | 1 |
| 2018 | 2 |
| 2017 | 5 |
| 2016 | 4 |
| 2015 | 1 |
| 2014 | 2 |