TL;DR: A 3.3 V-only 32 Mb NAND flash memory that achieves not only high performance but also low cost with a 94.9 mm/sup 2/ die size, improved yields, and a simple process with 0.5 /spl mu/m CMOS technology is described.
Abstract: While the performance of flash memory exceeds hard disk drives in almost every category, the cost of flash memory must come down in order to gain wider acceptance in mass storage applications. This paper describes a 3.3 V-only 32 Mb NAND flash memory that achieves not only high performance but also low cost with a 94.9 mm/sup 2/ die size, improved yields, and a simple process with 0.5 /spl mu/m CMOS technology. Die size is reduced by eliminating high voltage operation on the bitlines through a self boosted program inhibit voltage generation scheme. Incremental-step-pulse programming results in a 2.3 MB/s program data rate as well as improved process variation tolerance. Interleaved data paths and a boosted wordline results in a 25 ns burst cycle time and a 24 MB/s read data rate. Maximum operating current is less than 8 mA.
TL;DR: The electronic casino gaming system consists of several system components, including a microprocessor (12), a main memory unit (13) that is typically a random access memory, and a system boot ROM (14) as discussed by the authors.
Abstract: The electronic casino gaming system consists of several system components, including a microprocessor (12), a main memory unit (13) that is typically a random access memory, and a system boot ROM (14). Also included in the electronic casino gaming system are a non-volatile RAM (17), a mass storage unit (18), a disk subsystem (19), and a PCI bus (20). The disk subsystem (19) preferably supports SCSI-2 with options of fast and wide. A video subsystem (22) is also included in the electronic casino gaming system and is coupled to the PCI bus (20) to provide full color still images and MPEG movies.
TL;DR: In this article, the mass storage subsystem stores information on a series of tracks and allows the host computer to determine whether the bit associated with the track in which the information is to be stored is set and, if so, enable the host to back up the track out of turn, and to re-set the track's bit.
Abstract: A computer system includes a host computer, a mass storage subsystem and a backup subsystem for backing up information stored on the mass storage subsystem. The mass storage subsystem stores information on a series of tracks. A backup bit map includes a plurality of bits each associated with a respective one of the tracks and indicates the backup status of the track during a backup operation. Initially, during a backup operation, the bits associated with the tracks to be backed up will be set. Generally, the mass storage subsystem transfers information from the track to be backed up in order of the bits in the bit map, and after each track is backed up, it will clear the track's bit. However, when the host is to store information in the mass storage subsystem, it will determine whether the bit associated with the track in which the information is to be stored is set and, if so, enable the mass storage subsystem to back up the track out of turn, and to re-set the track's bit. After the information has been retrieved from the track, the bit associated therewith will be reset, and the host will store the information in the track. This allows the mass storage subsystem to ensure that the backed up information will correspond to the information as of the beginning of the backup operation, and in addition will allow the host to continue operations during the backup operation.
TL;DR: In this paper, a data buffer is coupled to a mass storage unit for storing up to M of the temporally-ordered segments, wherein M is less than N. The data buffer manager schedules the transfers in accordance with at least a predicted time that an individual one of temporally ordered segments will be required to be output from the data buffer.
Abstract: A data storage system includes a mass storage unit storing a data entity, such as a digital representation of a video presentation, that is partitioned into a plurality N of temporally-ordered segments. A data buffer is bidirectionally coupled to the mass storage unit for storing up to M of the temporally-ordered segments, wherein M is less than N. The data buffer has an output for outputting stored ones of the temporally-ordered segments. The data storage system further includes a data buffer manager for scheduling transfers of individual ones of the temporally-ordered segments between the mass storage unit and the data buffer. The data buffer manager schedules the transfers in accordance with at least a predicted time that an individual one of the temporally-ordered segments will be required to be output from the data buffer. When employed with a media streamer (10) distributed data buffer management techniques are employed for selecting blocks to be retained in a buffer memory, either in a storage node (16, 17) or in a communication node (14). These techniques rely on the predictable nature of the video data stream, and thus are enabled to predict the future requirements for a given one of the data blocks.
TL;DR: It is shown empirically that the IPL approach can yield considerable performance benefit over traditional design for disk-based database servers, and that the basic design of IPL can be elegantly extended to support transactional database recovery.
Abstract: The popularity of high-density flash memory as data storage media has increased steadily for a wide spectrum of computing devices such as PDA's, MP3 players, mobile phones and digital cameras. More recently, computer manufacturers started launching new lines of mobile or portable computers that did away with magnetic disk drives altogether, replacing them with tens of gigabytes of NAND flash memory. Like EEPROM and magnetic disk drives, flash memory is non-volatile and retains its contents even when the power is turned off. As its capacity increases and price drops, flash memory will compete more successfully with lower-end, lower-capacity disk drives. It is thus not inconceivable to consider running a full database system on the flash-only computing platforms or running an embedded database system on the lightweight computing devices. In this paper, we present a new design called in-page logging (IPL) for flash memory based database servers. This new design overcomes the limitations of flash memory such as high write latency, and exploits unique characteristics of flash memory to achieve the best attainable performance for flash-based database servers. We show empirically that the IPL approach can yield considerable performance benefit over traditional design for disk-based database servers. We also show that the basic design of IPL can be elegantly extended to support transactional database recovery.