Mask

Abstract: Classification of packets into flows is an inherent operation performed by networks that support enhanced services To support multiple-dimensional packet classification, a packet classification system is provided to select representative bits from a packet to look up a set of rules The per-flow classification works with a large set of rules, where each rule comprises of multiple fields and also allows fast dynamic variation in the rule set A lookup process includes a simple and finite set of instructions that can be efficiently implemented as pipelined hardware and support very high packet arrival rates

Abstract: Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.

Abstract: Various systems and methods for performing bit indexed explicit replication (BIER). For example, one method involves receiving a packet at a node. The packet includes a bit string. The node selects forwarding information based on a flow value associated with the packet. The forwarding information includes a forwarding bit mask. The node then forwards the packet based on the bit string and the forwarding information.

Abstract: A variable field partial write system for merging data bits in a memory word or words upon programmable request is described. The variable bit field can be selected for any number of bit positions from a single bit up to and including a full data word, where data words are comprised of a predetermined number of bytes each containing a predetermined number of bits. A starting bit code defines the location of the start of the bit field to be written and a field length code defines the number of bits that are to be merged and written. The combination of the starting bit code and the field length code define the ending bit control for the bits to be written, and are further utilized to control word boundary crossing into the next sequentially addressed memory word when the bit field to be written cannot be completed in the addressed word. Mask signals are generated for all bit positions that precede the starting bit code and that follow the ending bit code so that bit positions of data words read from memory that correspond to the mask bits are merged unaltered with the variable field bits that are to be written and the merged data words are thereafter returned for storage in the memory system. Bit mask signals are generated for all like-ordered bits in each byte and byte mask signals are generated to enable setting of mask configurations for all bytes in which at least one bit is to remain unaltered, through the use of decode and translator circuits coupled to control bit mask circuits and byte mask circuits.