Topic
Logic simulation
About: Logic simulation is a research topic. Over the lifetime, 2383 publications have been published within this topic receiving 32946 citations.
Papers published on a yearly basis
1 / 2
Papers
12 Nov 2011
TL;DR: Interval simulation provides a balance between detailed cycle-accurate simulation and one-IPC simulation, allowing long-running simulations to be modeled much faster than with detailed cycle, while still providing the detail necessary to observe core-uncore interactions across the entire system.
Abstract: Two major trends in high-performance computing, namely, larger numbers of cores and the growing size of on-chip cache memory, are creating significant challenges for evaluating the design space of future processor architectures. Fast and scalable simulations are therefore needed to allow for sufficient exploration of large multi-core systems within a limited simulation time budget. By bringing together accurate high-abstraction analytical models with fast parallel simulation, architects can trade off accuracy with simulation speed to allow for longer application runs, covering a larger portion of the hardware design space. Interval simulation provides this balance between detailed cycle-accurate simulation and one-IPC simulation, allowing long-running simulations to be modeled much faster than with detailed cycle-accurate simulation, while still providing the detail necessary to observe core-uncore interactions across the entire system. Validations against real hardware show average absolute errors within 25% for a variety of multi-threaded workloads; more than twice as accurate on average as one-IPC simulation. Further, we demonstrate scalable simulation speed of up to 2.0 MIPS when simulating a 16-core system on an 8-core SMP machine.
941 citations
TL;DR: A formal theory of MOS logic circuits is developed starting from a description of circuit behavior in terms of switch graphs and an algorithm for a logic simulator based on the switch-level model which computes the new state of the network by solving a set of equations in a simple, discrete algebra.
Abstract: The switch-level model describes the logical behavior of digital systems implemented in metal oxide semiconductor (MOS) technology. In this model a network consists of a set of nodes connected by transistor "switches" with each node having a state 0, 1, or X (for invalid or uninitialized), and each transistor having a state "open," "closed," or "indeterminate." Many characteristics of MOS circuits can be modeled accurately, including: ratioed, complementary, and precharged logic; dynamic and static storage; (bidirectional) pass transistors; buses; charge sharing; and sneak paths. In this paper we present a formal development of the switch-level model starting from a description of circuit behavior in terms of switch graphs. Then we describe an algorithm for a logic simulator based on the switch-level model which computes the new state of the network by solving a set of equations in a simple, discrete algebra. This algorithm has been implemented in the simulator MOSSIM II and operates at speeds approaching those of conventional logic gate simulators. By developing a formal theory of MOS logic circuits, we have achieved a greater degree of generality and accuracy than is found in other logic simulators for MOS.
392 citations
TL;DR: Interval temporal logic offers a natural basis for the specification of devices and digital signals and is suitable for hardware description languages based on formalisms suited to temporal reasoning.
Abstract: Because digital systems operate over time, hardware descriptions should be based on formalisms suited to temporal reasoning. One such notation, interval temporal logic, offers a natural basis for the specification of devices and digital signals. As computer systems continue to grow in complexity, the distinction between hardware and software is becoming increasingly blurred. This situation has produced an increasing awareness of the need for behavioral models suited to specifying and reasoning about both digital devices and programs. Contemporary hardware description languages (for example, Barbacci, Parker and Wallace,2 and Su et al. 3) are not sufficient because of various limitations:
376 citations
10 Nov 2002
TL;DR: A new hybrid ASIC/FPGA chip architecture that is being developed in collaboration between IBM and Xilinx is introduced, and some of the design challenges this offers for designers and CAD developers are highlighted.
Abstract: This paper introduces a new hybrid ASIC/FPGA chip architecture that is being developed in collaboration between IBM and Xilinx, and highlights some of the design challenges this offers for designers and CAD developers. We review recent data from both the ASIC and FPGA industries, including technology features, and trends in usage and costs. This background data indicates that there are advantages to using standard ASICs and FPGAs for many applications, but technical and financial considerations are increasingly driving the need for a hybrid ASIC/FPGA architecture at specific volume tiers and technology nodes. As we describe the hybrid chip architecture ,we point out evolving tool and methodology issues that will need to be addressed to enable customers to effectively design hybrid ASIC/FPGAs. The discussion highlights specific automation issues in the areas of logic partitioning, logic simulation, verification, timing, layout and test.
346 citations
Book•
4 Nov 1996TL;DR: This book focuses on the ever-evolving applications of basic computer design concepts with strong connections to real-world technology.
Abstract: Featuring a strong emphasis on the fundamentals underlying contemporary logic design using hardware description languages, synthesis, and verification, this book focuses on the ever-evolving applications of basic computer design concepts with strong connections to real-world technology. Treatment of logic design, digital system design, and computer design. Ideal for self-study by engineers and computer scientists.
304 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2025 | 1 |
| 2024 | 2 |
| 2023 | 7 |
| 2022 | 6 |
| 2021 | 6 |
| 2020 | 11 |