Topic
Logic analyzer
About: Logic analyzer is a research topic. Over the lifetime, 780 publications have been published within this topic receiving 8109 citations.
Papers published on a yearly basis
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Papers
Patent•
19 Jan 1993TL;DR: In this article, a system for inserting code markers for observing indications (external to the microprocessor upon which the software operates) of the occurrence of an event in the execution of the software.
Abstract: A system (Figure 10) for inserting code markers for observing indications (external to the microprocessor upon which the software operates) of the occurrence of an event in the execution of the software. Additional instructions or markers are added to the software to be debugged to produce simple, encoded, memory references to otherwise unused memory or I/O locations that will always be visible to a logic analyzer as bus cycles. Although the code markers cause a minimal intrusion in the underlying software, they make tracing events by a conventional logic analyzer much simpler and allow for performance evaluations in manners not heretofore possible. In particular, the inserted code markers provide a method of dynamically extracting information from a running host or real-time "black box" embedded system (902) under test using simple low intrusion print statements, encoded I/O writes on procedure entries and exits, and/or an interface to service calls and the like which writes out the passed parameters. Generally, the code markers are inserted at compile time or interactively during the debug session to make visible critical points in the code execution, such as function calls, task creation, semaphore operations and other resource usage so as to speed isolation of problems at test points during debugging. Performance analysis and event analysis use the code markers of the invention to cut through the ambiguities of microprocessor prefetch and cache operations. Because of these features, the invention is particularly advantageous for use by software design teams developing complex embedded host or real-time operating systems using multi-task operating systems and/or object oriented systems.
290 citations
Patent•
18 Nov 1998TL;DR: In this paper, an electronic design automation (EDA) software tool running on a computer system allows signals to be captured both before and after a trigger condition (breakpoint) in a programmable logic device.
Abstract: Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint. The EDA tool directs the logic analyzer to unload the data from its capture buffer for display on a computer. The breakpoint and sample number can be changed without recompiling. A JTAG port controls the logic analyzer. Inputs and outputs of the logic analyzer are routed to unbonded JTAG-enabled I/O cells. Alternatively, a user-implemented test data register provides a JTAG-like chain of logic elements through which control and output information is shifted. Stimulus cells provide control information to the logic analyzer, and sense cells retrieve data from the logic analyzer.
244 citations
14 Nov 1967
TL;DR: In this article, the authors defined logic faults as "permanent or transient deviations of logic variables from the values specified in design." They also defined the concept of logic faults in hardware.
Abstract: Reliable performance of hardware has been a requirement for digital systems since the construction of the first digital computer. Improper functioning of the logic circuits in a digital system is manifested by logic faults, which are defined for this paper as "permanent or transient deviations of logic variables from the values specified in design."
193 citations
Patent•
18 May 1998TL;DR: In this article, a hardware emulation system is described, which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board, and the logic circuits necessary for executing logic analyzer functions are programmed into programmable resources in the logic chips of the emulation system.
Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into th e programmable resources in the logic chips of the emulation system.
180 citations
Patent•
27 Oct 1997TL;DR: In this article, the authors propose a technique for embedding a logic analyzer in a programmable logic device (PLD), which allows debugging of such a device in its actual operating conditions.
Abstract: A technique for embedding a logic analyzer in a programmable logic device allows debugging of such a device in its actual operating conditions. A logic analyzer circuit is embedded within a PLD, it captures and stores logic signals, and it unloads these signals through an interface to be viewed on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, specifies the number of samples to be stored, and specifies a system clock signal and a trigger condition that will begin the acquisition of data. The EDA tool then automatically inserts the logic analyzer circuit into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool communicates with the embedded logic analyzer in order to arm the circuit and to poll it until an acquisition has been made. The EDA tool then directs the logic analyzer to unload the data from its capture buffer and then displays the data on the computer. The logic analyzer circuit may then be rearmed to capture another sequence of sample values. The trigger condition may be changed without recompiling. The design may be recompiled with new logic analyzer parameters to debug a different portion.
172 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
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| 2025 | 2 |
| 2024 | 1 |
| 2023 | 3 |
| 2022 | 5 |
| 2021 | 5 |
| 2020 | 13 |