Topic
Layout Versus Schematic
About: Layout Versus Schematic is a research topic. Over the lifetime, 885 publications have been published within this topic receiving 13894 citations.
Papers published on a yearly basis
Papers
TL;DR: This paper discusses some layout adjustment methods and the preservation of the 'mental map' of the diagram, and two kinds of layout adjustments are described, an algorithm for rearranging a diagram to avoid overlapping nodes and a method aimed at changing the focus of interest of the user without destroying the mental map.
Abstract: Many models in software and information engineering use graph representations; examples are data flow diagrams, state transition diagrams, flow charts, PERT charts, organization charts, Petri nets and entity-relationship diagrams. The usefulness of these graph representations depends on the quality of the layout of the graphs. Automatic graph layout, which can release humans from graph drawing, is now available in several visualization systems. Most automatic layout facilities take a purely combinatorial description of a graph and produce a layout of the graph; these methods are called 'layout creation' methods. For interactive systems, another kind of layout is needed: a facility which can adjust a layout after a change is made by the user or by the application. Although layout adjustment is essential in interactive systems, most existing layout algorithms are designed for layout creation. The use of a layout creation method for layout adjustment may totally rearrange the layout and thus destroy the user's 'mental map' of the diagram; thus a set of layout adjustment methods, separate from layout creation methods, is needed. This paper discusses some layout adjustment methods and the preservation of the 'mental map' of the diagram. First, several models are proposed to make the concept of 'mental map' more precise. Then two kinds of layout adjustments are described. One is an algorithm for rearranging a diagram to avoid overlapping nodes, and the other is a method aimed at changing the focus of interest of the user without destroying the mental map. Next, some experience with visualization systems in which the techniques have been employed is also described.
662 citations
Patent•
14 Jun 1993TL;DR: In this article, the authors present a system for interactive design, synthesis and simulation of an electronic system allowing a user to design a system either by specification of a behavioral model in a high level language such as VHDL or by graphical entry.
Abstract: A system for interactive design, synthesis and simulation of an electronic system allowing a user to design a system either by specification of a behavioral model in a high level language such as VHDL or by graphical entry. The user can view full or partial simulation and design results simultaneously, on a single display window. The synthesis process uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is generally a series of transformations operating upon various levels of design representations. At each level, the design can be simulated and reviewed in schematic diagram form. The simulation results can be displayed immediately adjacent to signal lines on the diagram to which they correspond. In one embodiment, design rule violations are processed by an expert system to suggest possible corrections or alterations to the design which will eliminate the design rule violations. Schematic diagram and simulation displays showing those portions of the electronic system and simulated signal patterns which are related to the design rule violations are used to help the user identify and appropriately correct problems in the design.
367 citations
Patent•
30 Sep 1997
TL;DR: In this article, a method and system for performing layout verification on an integrated circuit (IC) design using reusable sub-designs is presented, where unchanged subdesigns of a hierarchical IC design can be reused upon subsequent verification processes of the same IC design.
Abstract: A method and system for performing layout verification on an integrated circuit (IC) design using reusable subdesigns. Many custom designed integrated circuits are designed and fabricated using a number of computer implemented automatic design processes. Within these processes, a high level design language (e.g., HDL or VHDL) description of the integrated circuit can be translated by a computer system into a netlist of technology specific gates and interconnections there between. The cells of the netlist are then placed spatially in an integrated circuit layout and the connections between the cells are routed using computerized place and route processes. Circuit designers next run layout verification tests on the layout to verify that the geometry and connectivity data of the design meets specific design rules and matches logically with the schematic representation. The present invention provides a method of layout verification where unchanged subdesigns of a hierarchical IC design can be reused upon subsequent verification processes of the same IC design. They are reused for both design rule checking (DRC) and layout versus schematic (LVS) comparison. By reusing some of the subcell designs, subsequent verification processes of the present invention can be performed very efficiently. To account for faults attributed to subcell interfaces, the present invention advantageously determines subcell overlap areas within the layout and selectively flattens and verifies these areas in addition to any subcell designs that were not previously validated. Further, the invention determines updated connectivity information for new subcell designs.
293 citations
Patent•
18 Feb 2005
TL;DR: In this paper, a system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts through generation of hierarchical design rules which capture localized layout requirements, and these adjusted design rules are then used to perform localized layout manipulation and mask data conversion.
Abstract: A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts through generation of hierarchical design rules which capture localized layout requirements. In contrast to conventional techniques which apply global design rules, the disclosed IC design system and method partition the original design layout into a desired level of granularity based on specified layout and integrated circuit properties. At that localized level, the design rules are adjusted appropriately to capture the critical aspects from a manufacturability standpoint. These adjusted design rules are then used to perform localized layout manipulation and mask data conversion.
228 citations
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TL;DR: A general overview of circuit layout, taking a unified approach to various styles of integrated circuits, printed circuit boards, and hybrid circuits, and problems associated with the implementation of a hierarchical system are discussed.
Abstract: This paper gives a general overview of circuit layout, taking a unified approach to various styles of integrated circuits, printed circuit boards, and hybrid circuits. A lot of attention is given to the layout of large and complicated circuits, in particular, to the layout of very-large-scale-integration (VLSI) chips. Though the paper is an overview, and one could almost say a tutorial, it is intended for readers with some basic knowledge of what a circuit layout is and what some of the basic problems are. The main subjects discussed are: assignment of gates, placement methods, loose routing, final routing, and problems associated with the implementation of a hierarchical system. The emphasis is on new, not widely published methods, and on methods that seem to have potential for solving some of the current problems. Practical examples illustrate this rather personal account of circuit layout and sugsest where we may go from here.
225 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2021 | 2 |
| 2020 | 3 |
| 2019 | 9 |
| 2018 | 3 |
| 2017 | 18 |
| 2016 | 19 |