Topic
Itoh-Tsujii inversion algorithm
About: Itoh-Tsujii inversion algorithm is a research topic. Over the lifetime, 10 publications have been published within this topic receiving 114 citations.
Papers
TL;DR: High-performance and high-speed field-programmable gate array (FPGA) implementations of polynomial basis Itoh–Tsujii inversion algorithm (ITA) over GF(2 m) constructed by irreducible trinomials and pentanomials are presented and improvement in the proposed architecture in terms of speed and performance is verified.
Abstract: In this study high-performance and high-speed field-programmable gate array (FPGA) implementations of polynomial basis Itoh–Tsujii inversion algorithm (ITA) over GF(2 m ) constructed by irreducible trinomials and pentanomials are presented. The proposed structures are designed by one field multiplier and k -times squarer blocks or exponentiation by 2 k , where k is a small positive integer. The k -times squarer blocks have an efficient tree structure with low critical path delay, and the multiplier is based on a proposed high-speed digit-serial architecture with minimum hardware resources. Furthermore, to reduce the computation time of ITA, the critical path of the circuit is broken to finer path using several registers. The computation times of the structure on Virtex-4 FPGA family are 0.262, 0.192 and 0.271 µs for GF(2163), GF(2193) and GF(2233), respectively. The comparison results with other implementations of the polynomial basis Itoh–Tsujii inversion algorithm verify the improvement in the proposed architecture in terms of speed and performance.
32 citations
14 Mar 2011
TL;DR: A theoretical model for the Itoh-Tsujii finite field inversion algorithm (ITA) for any Galois field and fc-input LUT based FPGA (k > 3) is presented, which would aid a hardware designer to select the ideal design parameters quickly.
Abstract: Maximizing the performance of the Itoh-Tsujii finite field inversion algorithm (ITA) on FPGAs requires tuning of several design parameters. This is often time consuming and difficult. This paper presents a theoretical model for the ITA for any Galois field and fc-input LUT based FPGA (k > 3). Such a model would aid a hardware designer to select the ideal design parameters quickly. The model is experimentally validated with the NIST specified fields and with 4 and 6 LUT based FPGAs. Finally, it is demonstrated that the resultant designs of the Itoh-Tsujii Inversion algorithm is most optimized among contemporary works on LUT based FPGAs.
29 citations
TL;DR: This paper proposes a novel technique supported with theoretical analysis which reduces the critical delay of the ITA architecture without increasing the clock cycle requirement, and experimental results are presented to show that the proposed technique outperforms reported results.
17 citations
9 May 2014
TL;DR: This work presents an FPGA implementation of the multiplicative inversion for the key lengths of 194, 233, and 384- bits and uses Sunar-Koc multiplier for the finite field, GF(2m) multiplication.
Abstract: Elliptic Curve Cryptography (ECC) has been gaining popularity due to its shorter key size requirements. It uses arithmetic operations including addition, subtraction, multiplication and inversion in finite fields. For an efficient implementation of ECC, it is very important to carry out these operations faster using lesser resources. The in version operation consumes most of the time and more resources. The Itoh-Tsujii algorithm can be used to carry out the computation of multiplicative inverse by making use of Brauer addition chains in less time. This work presents an FPGA implementation of the multiplicative inversion for the key lengths of 194-, 233-, and 384- bits. A resource comparison for these key lengths is also made. This work uses Sunar-Koc multiplier for the finite field, GF(2 m ) multiplication.
5 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2021 | 1 |
| 2019 | 1 |
| 2018 | 1 |
| 2017 | 1 |
| 2014 | 1 |
| 2012 | 1 |