ITFET

Abstract: The scaling challenges of complementary metal oxide semiconductors (CMOS) are increasing with the pace of scaling showing marked signs of slowing down. This slowing has brought about a widespread search for an alternative beyond-CMOS device concept. While the charge tunneling phenomenon has been known for almost a century, and tunneling based transistors have been studied in the past few decades, its possibilities are being re-examined with the emergence of a new class of two-dimensional (2D) materials. By stacking varying 2D materials together, with two electrode layers sandwiching a tunnel dielectric layer, it could be possible to make vertical tunnel transistors without the limitations that have plagued such devices implemented within other material systems. When the two electrode layers are of the same material, under certain conditions, one can achieve resonant tunneling between the two layers, manifesting as negative differential resistance (NDR) in the interlayer current–voltage characteristics. We call this type of device an interlayer tunnel FET (ITFET). We review the basic operation principles of this device, experimental and theoretical studies, and benchmark simulation results for several digital logic gates based on a compact model that we developed. The results are placed in the context of work going on in other groups.

Abstract: A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises semiconductor substrate, a first layer of a first semiconductor material over the semiconductor substrate and a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material.

Abstract: The resonant tunneling characteristics of the inter-layer tunnel field-effect transistor (ITFET) within 2D van der Waals' materials can be made sharper by the use of multiple (m) intermediate well and tunnel barrier layers within a “mlTFET” variation. Ballistic quantum transport simulations are used to obtain the resonance characteristics in an MoS2 based-system, for specificity. Circuit simulations illustrate how the sharper resonance can lead to lower operating voltages and, thus, power, thereby improving the circuit performance.

Abstract: A variety of charge-based logic devices are being investigated as possible technology options for the beyond-CMOS era. The tunneling devices, such as the Bilayer Pseudo Spin Field Effect transistor (BiSFET), the Bilayer Pseudo Spin Junction Transistor (BiSJT) and the Interlayer Tunnel Field Effect Transistor (ITFET), have previously been studied for their logic capabilities. These have an intrinsic memory capability, making them an interesting candidate for standalone memory applications. The performance of these devices with respect to Complementary Metal Oxide Semiconductor (CMOS) for memory applications is presented.