Interrupt flag

Abstract: A CAN microcontroller that supports a plurality of uniquely-numbered message objects, that includes a processor core that runs CAN applications, a plurality of message buffers associated with respective ones of the message objects, and a CAN/CAL module. The CAN microcontroller further includes a plurality of individual message object registers associated with each message object, including at least one control register that contains an interrupt-enable control bit, a receive enable bit, and a transmit enable bit. The CAN microcontroller also includes a plurality of global message object control registers, including at least one message complete status register that contains a plurality of status flag bits for respective ones of the message objects, at least one interrupt flag register that contains a receive complete interrupt flag bit and a transmit complete interrupt flag bit, and a message complete info register that contains a plurality of message object identification bits and a status bit. The CAN/CAL module includes a message handling function that automatically transfers successive frames of an incoming multi-frame message to the message buffer associated with a corresponding message object; an end-of-message detection function that detects an end-of-message condition which occurs when the last frame of the accepted incoming multi-frame message has been stored in the message buffer associated with the corresponding message object; and, an end-of-message detection handling and interrupt generation function that, in response to the detection of the end-of-message condition: sets the status flag bit contained in the at least one message complete status register associated with the corresponding message object; sets the receive complete interrupt flag bit contained in the at least one interrupt flag register, if the interrupt-enable control bit contained in the at least one control register associated with the corresponding message object is set; and, sets the status bit contained in the message complete info register, if the interrupt-enable control bit contained in the at least one control register associated with the corresponding message object is set.

Abstract: An inter-processor communication system for a multi-processor environment wherein each processor has an associated processor system controller comprising an inter-processor communication registers (IPC Comm Reg). The IPC Comm Reg further comprising a response command register (CMD1 Reg), a non-response command register (CMD2 Reg), and a response register (RSP Reg). During inter-processor communication, the IPC Comm Reg of an initiating processor is coupled to the IPC Comm Reg of a target processor via the IPC bus so that data can be transmitted and one or more of a set of control flags of the target IPC Comm Reg is cleared or set in response to a write or read operation. In the inter-processor communication method for communication between multiple processors the initiating processor system controller coupled to an initiating processor detects the state of a set of status control flags of an initiating IPC Comm Reg associated with that initiating processor. In response to the detected state of the set of status control flags, the initiating system controller writes data to a remote target IPC Comm Reg of a remote target processor system controller, and also sets an associated interrupt flag in the target IPC Comm Reg in response to that write operation. The target system controller then detects the set interrupt flag in the target IPC Comm Reg, and in response thereto, reads data from the target IPC Comm Reg. Moreover, the initiating and/or target system controller may perform additional command sequence depending on the communication mode selected, i.e., auto-response method, CPU-response method, or non-response method.

Abstract: A data cartridge caddy presence sensing system within an autochanger storage rack is disclosed. The data cartridge caddy of the present invention has at least one optical interrupt flag at a predetermined position on the data cartridge caddy. When the data cartridge caddy is fully installed within the autochanger storage rack, the optical interrupt flag lines-up with and trips optical interrupt flags on the autochanger storage rack. The picker of the autochanger will not attempt to remove data cartridges from caddy positions that are empty. The present invention may also include optical interrupt flags and sensors on the data cartridges and corresponding optical interrupt sensors at corresponding predetermined locations on the autochanger storage rack or a bar-code reader and bar-code labels on the data cartridges. In such an embodiment, the autochanger picker will not attempt to remove data cartridges that are known to not be present within the data cartridge caddy and will not attempt to install a data cartridge in a slot in the data cartridge caddy that already has a data cartridge in it.

Abstract: In a non-volatile memory unit such as a flash memory unit, the degradation of charge can result in an error during a read operation. By using the error checking and correction techniques, a determination can be made whether a detected error can be corrected and, if correctable, is the consistent with charge degradation at that bit position displaying the error. When a correctable error is detected, the signal group address and the correction pattern are stored and an interrupt request flag applied to the central processing unit. When the interrupt flag is processed, the central processing unit, using the signal group address and the correction pattern, restores the charge of the bit position in the memory unit. In this manner, further read operations involving the restored bit position will not repeat the corrected error.