Interleave sequence

Abstract: A counter circuit selectively generates counting sequences in binary and interleave counting modes. A counter is formed by 3 toggle flip-flops. The toggle signals are provided by a toggle control circuit which contains logic gates that are enabled or disabled based on the state of a mode select signal. In binary mode, output bits are permitted to be used to toggle higher order count stages. In interleave mode, the binary toggle signals are blocked, and another counter circuit counts toggle signals in the interleave sequence, which signals are passed by the toggle control circuit to toggle inputs of the main counter. The other counter circuit can be reset in response to a reset signal applied to a load enable input.

Abstract: PROBLEM TO BE SOLVED: To obtain a turbo coder/decoder capable of parallelizing the decoding processing of a turbo code without being mounted with a memory which stores interleave sequences, a turbo coding/decoding method, and a communication system. SOLUTION: When a memory interface 5 generates an interleave sequence of the turbo code, interleave positions in forward direction processing and backward direction processing are calculated by only executing addition/subtraction processing and comparative computation processing by a control part 6. Thus, since memory access depending on the interleave sequences is sequentially obtained by simple calculation, the memory for holding the interleave system becomes unnecessary, and a memory amount and a circuit scale are minimized. COPYRIGHT: (C)2009,JPO&INPIT

Abstract: A counter circuit, which may be on a semiconductor integrated circuit, that is applicable to both a linear sequence and an interleave sequence and is capable of setting a burst length at 1, 2, 4, 8, or 2n in both sequences. The burst length of the counter circuit may be changeable, and the counter circuit may output a signal indicating whether the count number has reached the burst length.

Abstract: A programmable counter circuit for use in semiconductor memories for generating both sequential and interleave address sequences for block data accesses is disclosed. The output and complementary output of a burst counter circuit are multiplexed to send the proper carry bit information to the row/column counter of a memory device. In interleave mode, the carry bit is forced to match that of the burst counter, thus forcing the row/column counter of the memory device to count in an interleave address sequence. In sequential mode, the start address of the memory access is captured and held. Either the output or complementary output of the burst counter is used to control the column counter based on the captured start address bit. The counter can be programmed to automatically increment the memory address in both a binary and interleave sequence in order to increase the access speed for blocks of sequential data in semiconductor memories.