Abstract: Our latest developments in miniaturizing 3D printed microfluidics [Gong et al., Lab Chip, 2016, 16, 2450; Gong et al., Lab Chip, 2017, 17, 2899] offer the opportunity to fabricate highly integrated chips that measure only a few mm on a side. For such small chips, an interconnection method is needed to provide the necessary world-to-chip reagent and pneumatic connections. In this paper, we introduce simple integrated microgaskets (SIMs) and controlled-compression integrated microgaskets (CCIMs) to connect a small device chip to a larger interface chip that implements world-to-chip connections. SIMs or CCIMs are directly 3D printed as part of the device chip, and therefore no additional materials or components are required to make the connection to the larger 3D printed interface chip. We demonstrate 121 chip-to-chip interconnections in an 11 × 11 array for both SIMs and CCIMs with an areal density of 53 interconnections per mm2 and show that they withstand fluid pressures of 50 psi. We further demonstrate their reusability by testing the devices 100 times without seal failure. Scaling experiments show that 20 × 20 interconnection arrays are feasible and that the CCIM areal density can be increased to 88 interconnections per mm2. We then show the utility of spatially distributed discrete CCIMs by using an interconnection chip with 28 chip-to-world interconnects to test 45 3D printed valves in a 9 × 5 array. Each valve is only 300 μm in diameter (the smallest yet reported for 3D printed valves). Every row of 5 valves is tested to at least 10 000 actuations, with one row tested to 1 000 000 actuations. In all cases, there is no sign of valve failure, and the CCIM interconnections prove an effective means of using a single interface chip to test a series of valve array chips.

Abstract: With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs) will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave) wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC) and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications.

Abstract: Asynchronous interconnection of grids has advantage over synchronous interconnection in terms of fault clearance time, islanding operation and disturbance propagation. Presently, asynchronous interconnection of medium voltage microgrids is realized using AC-DC and DC-AC power converters with the galvanic isolation provided by the power frequency transformers connected to the grids. The converters are typically implemented using 3.3 kV–6.5 kV silicon IGBTs. In this paper, a novel topology is proposed for asynchronous interconnection of 13.8 kV grids enabled by series connection of latest Gen-3 10 kV, 15 A SiC MOSFETs. The asynchronous microgrid power conditioning system (AMPCS) uses three level neutral point clamped (3L-NPC) legs in AC-DC, DC-DC and DC-AC power stages. The DC-DC stage provides the galvanic isolation between the grids, and is realized by three phase dual active bridge (DAB). Simulation results are provided to validate the performance of the AMPCS in bidirectional power flow, low voltage ride through condition and interconnection of grids with different frequencies. The 3- L NPC leg is designed, fabricated and demonstrated experimentally at 2.5 kV dc bus and 10 kHz switching frequency in sine-triangle inverter mode.

Abstract: Fault tolerance is an important issue in interconnection networks, and the traditional edge connectivity is an important measure to evaluate the robustness of an interconnection network. The compon...

Abstract: This paper presents a compact integration design of a low-cost bondwire-interconnection scheme between a 60-GHz CMOS vital-signs Doppler radar sensor chip and a millimeter-wave patch-array planar antenna (17-dBi gain). The interconnection has the form of an inductance-capacitance-inductance structure configured as a T-matching network. It consists of a short microstrip line as a small capacitance and parallel bondwires as inductance. Open-ended stubs are additionally applied in the design to improve the ground connection at 60 GHz. To enhance the robustness of the impedance-matching bandwidth to withstand possible bonding length variations, additional series and shunt transmission lines are also deployed. The proposed low-cost integrated circuit-to-board interconnection design requires no additional processing (e.g., cavity etching of the carrier board). In the experimental measurement, compared with the radar sensor connected with a 7-dB-loss ${V}$ -band cable to the planar antenna in a previous report, the implemented compact bondwire-interconnected CMOS radar antenna module can enhance the detection range from 75 to at least 105 cm [and potentially up to 120–150 cm if the radar chip output power (0 dBm) is the same as 3 dBm]. This shows the potential facilitation for the incorporation of the 60-GHz radar sensor chip into portable devices for wireless remote physiological monitoring healthcare applications.

Abstract: Wireless interconnects have emerged as a solution to the problem of metallic interconnections for both intra and inter-chip communications. Multi GHz bandwidths of millimeter-wave (mm-wave) antennas coupled with appropriate system-level interconnection fabric design enables low power and high-speed communication between multiple many-core chips. In this paper, we discuss the design and transmission characteristics of an mm-wave antenna for multi-chip wireless interconnection systems. We investigate the challenges and opportunities for antenna design in this domain. We present a specific antenna design and its performance in terms of its transmission characteristics for inter-chip communication in a server node. Lastly, we explore the impact of antenna design on system-level design choices pertaining to Medium Access Control (MAC), topology and modulation techniques suitable for multi-chip systems.

Abstract: The ball grid array (BGA) structure is the interconnection between package to printed circuit board and the discontinuity from BGA affects the performance for the whole link path in the high-speed digital system. So, it is important to accurately model the BGA structures. In current methods, the current distribution of conductors is treated as isotropic. However, the pitch size of solder balls is comparable to the diameter. The current is no longer uniformly distributed. In this paper, a fast modal-based approach is developed to accurately and efficiently capture the proximity effect. Image theory is also applied in the proposed approach to reduce the computational domain from 3-D structure to 2-D. The matrix reduction approach is applied to obtain the physical loop inductance. The lumped capacitance is obtained in [1] . A $\pi $ topology equivalent circuit model for the BGA structure is built. Good agreement between the equivalent circuit model and full-wave simulation can be achieved up to 40 GHz.

Abstract: There has been an increasingly interest in the use of paper as inexpensive, foldable and disposable substrate material. In this paper, a novel pencil-on-paper strain sensor for flexible vertical interconnection is proposed. Graphite traces were used to fabricate the device. The strain changes would result in resistance changes depending on the graphite particles movement, thus, rotation strain can be detected. The sensor can also differentiate compressive and tensile signals. The proposed method presents a further expansion of fast and simple solution for realizing the full potential of paper substrate.

Abstract: Along with the recent surge in scale expansion of data centers, the interconnection scheme is facing a grave challenge. A huge amount of cables between the switches make the system maintenance and heat dissipation extremely difficult. A promising solution to this problem is using the arrayed waveguide grating (AWG), which can provide a set of wavelength links between its inputs and outputs. However, the scalability of the AWG-based interconnection scheme is restricted by the coherent crosstalk and the wavelength granularity of AWGs. In this paper, we propose a generic modular AWG-based interconnection scheme with scalable wavelength granularity for mega data centers. We first devise a matrix-based method to decompose the AWG into a three-stage network of smaller AWGs, while preserving the nonblocking wavelength routing property of the AWGs. We then introduce the concept of wavelength independency based on the partitioning of the optical connections, such that modular AWGs in the network can reuse the same wavelength set with smaller granularity. We show that the proposed modular AWG-based interconnection network can simplify the cabling complexity of data center networks, while preserving the same function and bandwidth as the original data center network.

Abstract: In this paper, a unique adaptive layout methodology for accurate interconnection between two or more functional chips at the wafer level is presented. The methodology is based on an automatic layout modification for each embedded chip with considering exact related offset and rotation after chip embedding. As a result, a wafer-level embedding and accurate interconnecting and integrating of ultrathin chips in the polymer are feasible. The significant application of the presented accurate interconnection between the groups of functional chips is the microhybrid system-in-foil. Also, an adaptive interconnect layout at wafer-level base, allowing for a small wire pitch on and off the chip, leads to reducing silicon area and, thus, saves cost. In this paper, the process flow for embedding and integrating chips based on the adaptive layout technique is presented. The custom designed test chips are processed for the measurement and optimization of overlay accuracy of the adaptive interconnect layout regardless of the chip thickness, warpage, and topography. Besides, the electrical measurements after integrating ultrathin chips in foil confirm the interconnection between chips.

Abstract: Offshore wind farm (OWF) is the largest renewable energy resource. The electrical interconnection cost of OWFs is a considerable fraction of the overall design cost of the farm. In order to minimize the investment and operational costs, this paper proposes an optimization formulation to find the optimal electrical interconnection configuration of wind turbines (WTs), and the optimal cable sizing simultaneously. This simultaneous minimization of total trenching length and cable dimensions creates a complex optimization problem that is solved by the harmony search (HS) algorithm. In this paper, two distinct methods of full and partial optimal cable sizing are considered to comprehensively assess the optimal interconnection layout of OWFs. Furthermore, various shipping and burying costs as well as various WTs power ratings are considered in order to investigate their impact on the optimal electrical interconnection system. The optimal electrical interconnection design obtained by the HS algorithm corresponds to a lower cost that together with the technological developments can help policy makers increase the use of offshore wind energy as a feasible unlimited renewable resource in their energy production portfolios.

Abstract: The incorporation of a micro copper pillar is considered as the major interconnection method in three-dimensional (3D) integrated circuit (IC) intergradation under high-density I/O conditions. To achieve low-temperature bonding, this study investigated the thermosonic flip chip bonding of a copper pillar with a tin cap. The effect of bonding force on bonding strength was studied, and an average bonding strength 2500 g (approximately 84.8 MPa) was obtained in 2 s, at an optimized bonding force of 0.11 N per 40 μm pillar bump, and substrate temperature of 200 °C. Additionally, the effect of the bonding force on bonding interface microstructure and intermetallic compounds (IMCs) was also investigated. Tin whiskers were also observed at the bonding interface at low bonding forces.

Abstract: We present an O-band any-to-any chip-to-chip (C2C) interconnection at 40 Gb/s suitable for up to 8-socket direct connectivity in multi-socket server boards, utilizing integrated low-energy photonics for the transceiver and routing functions. The C2C interconnect exploits an Si-based ring modulator as its transmitter and a co-packaged photodiode/transimpedance amplifier enabled receiver interconnected over an 8 x 8 Si-based arrayed waveguide grating router, allowing for a single-hop flat-topology interconnection between eight nodes. A proof-of-concept demonstration of the C2C interconnect is presented at 25 and 40 Gb/s for eight possible routing scenarios, revealing clear eye diagrams at both data rates with extinction ratios of 4.8 +/- 0.3 and 4.38 +/- 0.31 dB, respectively, among the eight routed signals.

Abstract: A telecommunications network comprises at least one core network interface for providing interconnection to a core network. At least one base station provides communications to at least one user device. At least one server defines a configurable network interconnecting at least one core network interface and the base station. The at least one server defines logically independent network slicing for the configurable network that selects a first network slice responsive to use of the configurable network by a first application and selects a second network slice responsive to use of the configurable network by a second application. The at least one server further provides a data center based cloud architecture to support the first network slice when the first application is selected and the second network slice when the second application is selected.

Abstract: We propose two-photon absorption light-induced self-written (LISW) waveguide formation using short-wavelength infrared pulse laser light. It is suitable and efficient for single-mode optical interconnection, and also promising for small-core single-mode optical interconnection. The approach offers the possibility of not only decreasing the insertion loss, but also reducing the interconnection task time. We assessed this approach for single-mode optical interconnection. We obtained an LISW waveguide loss of about 0.06 dB for an LISW waveguide length of 100 μ m and a connection loss per facet of about 0.37 dB. We also presented the results on the interconnection between high-numerical-aperture small-core thermally-diffused expanded-core single-mode fibers having the mode field diameters of about 3 μ m by using the same approach. The results showed the present approach to be a promising alternative route for efficient interconnection of small-core single-mode optical devices, such as silicon nanowires with appropriate configurations.

Abstract: Flexible displays and electronics are emerging technology. A PET substrate is one the strong candidate substrate materials for the applications, however, its low thermal stability limited its penetration depth in the market. We propose the interconnection process using laser and hybrid underfill as a technical solution to prevent the thermal deformation of a PET film during the interconnection process. The LED module array is successfully fabricated on a PET substrate using laser and hybrid underfill. The process features a very short cycle time and tiling process for the high throughput.

Abstract: This paper proposes a highly dense reconfigurable architecture that introduces via-switch device, which is a nonvolatile resistive-change switch and is used in crossbar switches. Via-switch is implemented in back-end-of-line layers only, and hence the front-end-of-line (FEoL) layers under the crossbar can be fully exploited for highly dense logic blocks. The proposed architecture uses the FEoL layers for fine-grained lookup tables and coarse-grained arithmetic/memory units for improving performance and compatibility with various applications. A case study of application mapping shows the proposed architecture can reduce the array area by 21.7%, thanks to the bidirectional interconnection. Thanks to $18F^{2}$ footprint and one order of magnitude lower resistivity of via-switch compared to MOS switch, the crossbar density is improved by up to $26\times $ and the delay and energy in the interconnection are reduced by 90% and 94% at 0.5-V operation.

Abstract: This paper presents a consensus-based distributed synchronization control method for microgrids with multiple points of interconnection. The proposed method can synchronize a microgrid at different points of interconnection using a common sparse communication network among its distributed generators. This functionality is critical for the networked operation of multiple microgrids in the future power systems. The proposed approach uses averaging and leader-follower modes of a commonly used consensus algorithm for multi-agent systems to achieve microgrid synchronization and smooth transition between the islanded and grid-connected modes at different interconnection points. The operation of the proposed distributed synchronization method is demonstrated on a microgrid with four inverters, each with an independent interconnection point to another microgrid or a bulk power system.

Abstract: The paper focuses on modular conveyors, mainly dedicated for the transport of parcel goods of various properties. Accent will also be put to their use in processes where the belt’s resistance to higher temperatures or to mechanical damage is required. The solution is aimed on the use for installation in larger transport units, production as well assembly lines. The proposal of the conveyor design allows to handle different line sections (bends, broken sections, etc.) using a single drive. The conveyor track will be solved with aim to the transport of goods (products) by means of automated trolleys. A proposal for the synchronization of the conveyor track with an automated handling device will be presented, which will ensure the final phase of the production chain, the relocation of production to the warehouse of finished products. The authors will focus on the calculation of subsequent intervals for automated means of handling as well on determining the capacity of the conveyor track.

Abstract: In multi-robot systems passive interconnections among agents are often exploited to achieve a desired and robustly stable cooperative behavior. Nevertheless, the passivity constraint limits the kinds of behaviors that can be achieved. In this paper, we exploit the concept of energy tank for building a novel generalized interconnection that allows to impose any kind of dynamic coupling between two passive systems in a flexible way while preserving the passivity of the overall coupled system. The proposed strategy is validated by simulations and experiments

Abstract: We present an electrical model developed with LTSPICE that simulates the performance of a string of cells with disconnections in the electrical circuit. In a previous contribution, we quantified experimentally how the module performance is affected when one or more ribbons are cut or disconnected between cells. The measurements were made on mini-modules (strings) of six cells, connected in series by three interconnection ribbons. Here, we use these experimental results to validate our model. Results show that our model is able to describe well the power reduction due to the interruption/removal of the cell interconnecting ribbons, and to reproduce the peculiar shape of the IV curves of a string affected by non-homogeneous distribution of the series resistance within some of the cells.

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.