Abstract: The purpose of this paper is to analyze the impact of interconnection inductances to overvoltage during turn-off transient of silicon carbide (SiC) devices. To understand the switching behavior of the SiC devices, the ringing and overshoots of the voltage caused by the device capacitance and interconnection inductances are considered. Parametric studies are conducted to compare the influences of printed circuit board (PCB) and packaging inductances on the peak turn-off overvoltage under various operating conditions. A prototype half-bridge buck converter with SiC MOSFETs is constructed for the experiments. Experimental results are shown to validate the simulation results.

Abstract: Graphical abstractDisplay Omitted HighlightsA quantum version of the multilayer self organizing neural network (MLSONN) architecture is proposed.Single qubit rotation gates are designated as the interconnection weights between the different layers.A quantum measurement at the output layer destroys the quantum states.The measured states use linear indices of fuzziness as the system errors.Applications reveal efficient performance over conventional counterpart. Several classical techniques have evolved over the years for the purpose of denoising binary images. But the main disadvantages of these classical techniques lie in that an a priori information regarding the noise characteristics is required during the extraction process. Among the intelligent techniques in vogue, the multilayer self organizing neural network (MLSONN) architecture is suitable for binary image preprocessing tasks.In this article, we propose a quantum version of the MLSONN architecture. Similar to the MLSONN architecture, the proposed quantum multilayer self organizing neural network (QMLSONN) architecture comprises three processing layers viz., input, hidden and output layers. The different layers contains qubit based neurons. Single qubit rotation gates are designated as the network layer interconnection weights. A quantum measurement at the output layer destroys the quantum states of the processed information thereby inducing incorporation of linear indices of fuzziness as the network system errors used to adjust network interconnection weights through a quantum backpropagation algorithm.Results of application of the proposed QMLSONN are demonstrated on a synthetic and a real life binary image with varying degrees of Gaussian and uniform noise. A comparative study with the results obtained with the MLSONN architecture and the supervised Hopfield network reveals that the QMLSONN outperforms the MLSONN and the Hopfield network in terms of the computation time.

Abstract: Supersystems are shown to provide enough computational power to solve complex problems on a real-time basis. In all these systems, the computational parallelism is obtained from multiple processors. Multistage interconnection networks (MINs) play a vital role on the performance of these multiprocessor systems. This paper introduces a new fault-tolerant MIN named as improved extra group network (IEGN). IEGN is designed by existing extra group (EGN) network, which is a regular multipath network with limited fault tolerance. IEGN provides four times more paths between any source---destination pairs compared with EGN. The performance of IEGN has been evaluated in terms of permutation capability, fault tolerance, reliability, path length, and cost. It has also been proved that the IEGN can achieve better results in terms of fault tolerance, reliability, path length and cost-effectiveness, in comparison to known networks, namely, EGN, augmented baseline network, augmented shuffle-exchange network, fault-tolerant double tree, Benes network, and Replicated MIN.

Abstract: Intercore communication in many-core processors presently faces scalability issues similar to those that plagued intracity telecommunications in the 1960s. Optical communication promises to address these challenges now, as then, by providing low latency, high bandwidth, and low power communication. Silicon photonic devices presently are vulnerable to fabrication and temperature-induced variability. Our fabrication and measurement results indicate that such variations degrade interconnection performance and, in extreme cases, the interconnection may fail to function at all. In this paper, we propose a reliability-aware design flow to address variation-induced reliability issues. To mitigate effects of variations, limits of device design techniques are analyzed and requirements from architecture-level design are revealed. Based on this flow, a multilevel reliability management solution is proposed, which includes athermal coating at fabrication-level, voltage tuning at device-level, as well as channel hopping at architecture-level. Simulation results indicate that our solution can fully compensate variations thereby sustaining reliable on-chip optical communication with power efficiency.

Abstract: Multistage interconnection networks (MINs) are widely used for reliable data communication in a tightly coupled large-scale multiprocessor system High reliability of MINs can be achieved using fault tolerance techniques The fault tolerance is generally achieved by disjoint paths available through multiple connectivity options The gamma interconnection network (GIN) is a class of fault tolerant MINs providing alternate paths for source---destination node pairs Various 2-disjoint and 3-disjoint GIN architectures have been presented in the literature In this paper, two new designs of 4-disjoint paths multistage interconnection networks, called 4-disjoint gamma interconnection networks (4DGIN-1 and 4DGIN-2) are proposed The proposed 4DGINs provide four disjoint paths for each source---destination pair and can tolerate three switches/link failures in intermediate interconnection layers Proposed designs are highly reliable GIN with higher fault-tolerant capability than other gamma networks at low cost Terminal pair reliabilities of proposed designs and various other 2-disjoint and 3-disjoint GINs are evaluated, analyzed and compared Reliability values of proposed designs are found higher

Abstract: High penetrations of PV on the distribution system can impact the operation of the grid and may require interconnection studies to prevent reliability problems. In order to improve the interconnection study process, the use of feeder zones and PV impact signatures are proposed to group feeders by allowable PV size as well as by their limiting factors for the interconnection. The feeder signature separates feeders into different impact regions with varying levels of PV interconnection risk, accounting for impact mitigation strategies and associated costs. This locational information improves the speed and accuracy of the interconnection screening process. The interconnection risk analysis methodology is based on the feeder and interconnection parameters such as: feeder type, feeder characteristics, and location and size of PV. PV impact signatures, hosting capacity, and feeder risk zones are demonstrated for four realistic distribution systems.

Abstract: The invention discloses a multi-DSP and multi-FPGA parallel processing system which comprises FPGAs, DSPs, ADs, a DA, DDR3s and power supply chips. An implement method of the multi-DSP and multi-FPGA parallel processing system includes the following five steps: (1) achieving PCIe interconnection between the FPGAs, (2) achieving PCIe interconnection between the FPGAs and the DSPs, (3) achieving SRIO interconnection between the FPGAs, (4) achieving SRIO interconnection between the FPGAs and the DSPs, and (5) achieving Hyperlink interconnection between the DSPs. The multi-DSP and multi-FPGA parallel processing system is high in parallel processing capacity, abundant in function and high in flexibility and extensibility, data transmission bottlenecks between processor chips are broken, and the multi-DSP and multi-FPGA parallel processing system is high in transportability and have the good practical value in the digital signal processing field.

Abstract: Electrohydrodynamic (EHD)-inkjet printing is a novel high resolution inkjet printing technology with the advantages of being a maskless, non-contact, direct-write and additive process. Its printing resolution exceeds by about two orders of magnitude in comparison to the conventional inkjet printing systems. It is used in the field of micro/nano manufacturing for patterning of large class of materials on a variety of substrates with the options to use either Drop-On- Demand (D-O-D) or continuous mode. Printable electronics especially flexible electronics is one of the many fields where this technology has a lot to offer as the same EHD-inkjet set- up can be used for electrospraying for thin film layer deposition, electrospinning for interconnection and EHD jetting for making electrodes. A lot of research has been carried out in the recent past to make its transition from a research tool to a commercial manufacturing process. Many challenges such as increasing the process throughput (i.e. the printing speeds) have to be overcome before the commercialization of this technology. Another major challenge is to develop a compact, affordable and user friendly test platform to further develop the process and associated applications. This review gives a brief account of the EHD-inkjet technology; the research activities carried out in recent years and the wide areas of applications of this technology. The working of the EHD-inkjet system along with the physics of the process has also been discussed in brief. Keywords—Drop-on-Demand (D-O-D),

Abstract: As FPGA capacity increases, a growing challenge is connecting ever-more components with the current low-level FPGA interconnect while keeping designers productive and on-chip communication efficient. We propose augmenting FPGAs with networks-on-chip (NoCs) to simplify design, and we show that this can be done while maintaining or even improving silicon efficiency. We compare the area and speed efficiency of each NoC component when implemented hard versus soft to explore the space and inform our design choices. We then build on this component-level analysis to architect hard NoCs and integrate them into the FPGA fabric; these NoCs are on average 20--23× smaller and 5--6× faster than soft NoCs. A 64-node hard NoC uses only ∼2p of an FPGA's silicon area and metallization. We introduce a new communication efficiency metric: silicon area required per realized communication bandwidth. Soft NoCs consume 4960 mm2/TBps, but hard NoCs are 84× more efficient at 59 mm2/TBps. Informed design can further reduce the area overhead of NoCs to 23 mm2/TBps, which is only 2.6× less efficient than the simplest point-to-point soft links (9 mm2/TBps). Despite this almost comparable efficiency, NoCs can switch data across the entire FPGA while point-to-point links are very limited in capability; therefore, hard NoCs are expected to improve FPGA efficiency for more complex styles of communication.

Abstract: A Midimew connected Mesh Network (MMN) is a MInimal DIstance MEsh with Wrap-around links network of multiple basic modules, in which the basic modules are 2D-mesh networks that are hierarchically interconnected for higher-level networks. In this paper, we present the architecture of the MMN, addressing of node, routing of message, and evaluate the static network performance of MMN, TESH, mesh, and torus networks. It is shown that the MMN possesses several attractive features, including constant degree, small diameter, low cost, small average distance, moderate bisection width, and high fault tolerant performance than that of other conventional and hierarchical interconnection networks. It is also shown that with the same node degree, arc connectivity, bisection width, and wiring complexity, the diameter and average distance of the MMN is lower than that of the TESH network.

Abstract: A method for processing a semiconductor device, the method including; providing a first semiconductor layer including first transistors; forming interconnection layers overlying the transistors, where the interconnection layers include copper or aluminum; forming a shielding heat conducting layer overlaying the interconnection layers; forming an isolation layer overlaying the shielding heat conducting layer; forming a second semiconductor layer overlying the isolation layer, and processing the second semiconductor layer at a temperature greater than about 400° C., where the interconnection layers are kept at a temperature below about 400° C.

Abstract: Distributed generation (DG) technology is spreading rapidly owing to advantages of clean environment, loss reduction and voltage improvement. Utilities in Pakistan are welcoming all generations to increase their supply capacity. Industries are installing DGs to meet their load requirements. In order to reduce energy bills, DGs are being used to supply spare power back to utility or even in off peak durations. DG interconnection changes electrical network characteristics of existing utility network. Protection problems may occur in the form of relay settings, islanding and increased short circuit currents. This paper investigates the effects of DG interconnection on short circuit currents. A feeder of SITE industrial area of Karachi is modeled and simulated for short circuit analysis. Analysis shows that DG interconnection to a radial feeder increases short circuit level at all nodes of the feeder.

Abstract: In this paper, we present a temperature-dependent network model of a concentrator photovoltaic (CPV) module. The ability of this network model to calculate different interconnection schemes within CPV modules is validated, and there is good agreement between the measured and calculated data. The model is used to quantify the influence of an inhomogeneous current and of a temperature distribution between the solar cells on the power output of a module. The different interconnection schemes that combine parallel and series connections are compared. The optimal interconnection scheme strongly depends on the variations in the short current densities and temperature differences between the solar cells as well as on the risk of ‘sudden death’ of individual solar cells. Optimal interconnection schemes for several scenarios are developed. A combination of parallel and series interconnections is found to be the most robust interconnection. Copyright © 2012 John Wiley & Sons, Ltd.

Abstract: Polymer low-k materials have been considered in literature to meet the requirements of lowering the dielectric constant of the dielectric layer to decrease the problem of signal delay, lower power consumption, and reduce cross-talk between the neighboring paths, as well as, lower the fabrication temperature budget. In this paper, the feasibility of using Parylene-HT as a low-temperature deposition intelever dielectric in 3D interconnection is investigated and the results are presented. In particular, the diffusivities of Cu in room temperature deposited high-uniformity coverage Parylene-HT at 250 o C and 350 o C are evaluated to be 5.7E-18 cm 2 /s and 1.3E-16 cm 2 /s respectively, by dynamic secondary ion mass spectrometry (D-SIMS) technique. In addition, the capability of embedding Parylene-HT in through-Si-via (TSV) fabrication process through the demonstration of 36-μm-diameter 100-μm-depth copper-filled TSVs using Parylene-HT as a liner, are reported.

Abstract: Methods and systems for interconnecting circuit components with track patterns are disclosed. The method identifies a source pin on a first track and a destination pin on a second track and determines a third track in a different routing direction based on design rules governing track patterns. The method further determines a transition pattern for the interconnection between the source pin and the destination pin by using at least the third track. The method may use one or more dummy pins or ordering of pin connections in implementing the interconnection to satisfy certain design rules. The lengths of some wire segments of the interconnection may be further adjusted to satisfy certain design rules. Compaction may be performed to have two wire segments share the same track while the lengths or widths of one or both wire segments may be further modified to ensure design rule compliance.

Abstract: Interconnection meter socket adapters are provided. An interconnection meter socket adapter comprises a housing enclosing a set of electrical connections. The interconnection meter socket adapter may be configured to be coupled to a standard distribution panel and a standard electric meter, thereby establishing connections between a distribution panel and a user such that electrical power may be delivered to the user while an electrical meter measures the power consumption of the user. An interconnection meter socket adapter may be configured to be coupled to a DC-AC inverter, which may be coupled to various energy sources. As such, the energy sources are coupled to an electrical power system. In addition, a connector such as a flexible cable or flexible conduit containing insulated wires can be provided for connecting various energy sources and/or sinks.

Abstract: Provided is a memory card. The memory card includes interconnection terminals for electric connection with an external electronic machine. The interconnection terminals may be spaced from the front side of the memory card by a distance greater than the lengths of the interconnection terminals. Alternatively, the memory card may include other interconnection terminals between its front side and the former interconnection terminals. The former and latter interconnection terminals may be used for electric connection with different kinds of electronic machines.

Abstract: An interconnection verification device for sensors and a software implementation of interconnection verification between cabling and sensors in large, multi-channel test configurations are disclosed. In a preferred embodiment the sensor assembly comprises a sensor and an indicator electrically connected inline with the sensor. In a preferred embodiment the indicator is an LED. In an even more preferred embodiment, the sensor is an IEPE.

Abstract: According to one embodiment, a non-volatile memory device includes a memory cell array and a coil provided closely to the memory cell array. The memory cell array includes memory cells provided above an underlying layer, and a first interconnection. The memory cells are aligned in a first direction perpendicular to the underlying layer. The first interconnection extends in a second direction perpendicular to the first direction. The coil includes a winding including a second interconnection extending in the second direction and sharing a central axis with the first interconnection, a first plug extending in the first direction and connected to the second interconnection, a third interconnection electrically connected to another end of the first plug and extending in a direction parallel to the underlying layer, and a second plug having one end electrically connected to the third interconnection, and extending in a direction opposite to the first direction.

Abstract: Mesh and its variants are most simple and popular interconnection networks in the research community. Based on the 2D diagonal mesh a new interconnection topology called a modified diagonal mesh interconnection network (MDMIN) has been proposed. The proposed topology performs better than the simple 2D Mesh and diagonal (toroidal) mesh interconnection networks and also overcomes its drawbacks.

Abstract: The invention discloses a low-cost interconnection system of a mobile phone and a vehicle machine. The interconnection system comprises the mobile phone and the vehicle machine, wherein the vehicle machine comprises a vehicle-mounted radio and a speaker; at least one APP program is arranged on the cell phone, the vehicle machine further comprises a Bluetooth interconnection module, a Bluetooth interconnection key and a microphone; a communication connection between the vehicle-mounted radio and the mobile phone is established through the Bluetooth interconnection module; a Bluetooth connection between the mobile phone and the vehicle-mounted radio is established to implement bidirectional control, and an audio signal output by the mobile phone is played through the speaker; the Bluetooth interconnection key is connected to the vehicle-mounted radio, the microphone is connected to the Bluetooth interconnection module, when the Bluetooth interconnection key is pressed, the microphone is connected to the mobile phone through the Bluetooth interconnection module, the microphone is used for collecting voice sent by a user, converting the voice to a control command, and transmitting the control command to the mobile phone through the Bluetooth interconnection module, and the mobile phone opens the corresponding APP program on the mobile phone based on the control command. According to the low-cost interconnection system, sharing of mobile phone hardware, vehicle machine hardware and software resources can be implemented.

Abstract: The invention discloses interconnection and interworking and multi-screen interaction equipment, system and implementation method. The equipment comprises a central processor, a power manager, a WIFI module and an HDMI interface, wherein the power manager, the WIFI module and the HDMI interface are connected with the central processor. A display terminal is connected with the equipment through the HDMI interface, the equipment is in wireless connection with an intelligent terminal through the WIFI module, the intelligent terminal sends information to be shared to the equipment through the WIFI module, and the information is subjected to decoding processing by the central processor of the equipment and transmitted to the display terminal for display through the HDMI interface. According to the interconnection and interworking and multi-screen interaction equipment, system and implementation method, the advantages of each terminal are fully utilized, resources are shared, convenience is brought to users, meanwhile, cost is lowered, and use experience of the users is improved.