Abstract: An ultra-low-inductance power module using silicon carbide (SiC) devices has been developed by using an advanced packaging technology. The switching cell inductance was reduced significantly due to the absence of bond wires for chip interconnection. This was achieved by using PCB technologies on a DCB substrate to provide more interconnection layers and design freedom. The test result after fabrication showed the superiority of advanced packaging methods relating to switching behaviour. Almost no overshoot voltage and no ringing during turn-off were detected. The measured switching cell inductance went below 1nH which allows high speed switching and/or high efficiency applications by virtue of low switching losses.

Abstract: A high temperature, wire-bondless power electronics module with a double-sided cooling capability is proposed and successfully fabricated. In this module, a low-temperature co-fired ceramic (LTCC) substrate was used as the dielectric and chip carrier. Conducting vias were created on the LTCC carrier to realize the interconnection. The absent of a base plate reduced the overall thermal resistance and also improved the fatigue life by eliminating a large-area solder layer. Nano silver paste was used to attach power devices to the DBC substrate as well as to pattern the gate connection. Finite element simulations were used to compare the thermal performance to several reported double-sided power modules. Electrical measurements of a SiC MOSFET and SiC diode switching position demonstrated the functionality of the module.

Abstract: The topology of interconnection networks plays a key role in the performance of parallel computing systems. A new interconnection network called exchanged crossed cube (ECQ) is proposed and analyzed in this paper. We prove that ECQ has the better properties than other variations of the basic hypercube in terms of the smaller diameter, fewer links, and lower cost factor, which indicates the reduced communication overhead, lower hardware cost, and more balanced consideration among performance and cost. Furthermore, it maintains several attractive advantages including recursive structure, high partitionability, and strong connectivity. Furthermore, the optimal routing and broadcasting algorithms are proposed for this new network topology.

Abstract: In this paper, a liquid cooling solution has been reported for 3-D package in package-on-package format. A high heat dissipating chip is mounted on a silicon carrier, which has copper through-silicon via (TSV) for electrical interconnection and hollow TSV for fluidic circulation. Heat transfer enhancement structures have been embedded in the chip carrier. Cooling liquid, de-ionized water is circulated through the chip carrier and heat from the chip is extracted. The fluidic channels are isolated from electrical traces using hermetic sealing. The research work has demonstrated liquid cooling solution for 100 W from one stack and total of 200 W from two stacks of the package. The fluidic interconnections and sealing techniques have been discussed.

Abstract: With increasing connections of distributed rooftop PV to the distribution system, a method for simplifying the complex system to an equivalent representation of the feeder is useful to streamline the interconnection impact studies. This paper presents a method of reducing feeders to specified buses of interest while retaining equivalent electrical characteristics of the system. These buses of interest can be potential interconnection locations or buses where distribution engineers want to evaluate circuit performance. A methodology is presented showing equivalence of the reduction method with supporting equations and examples. Validation is performed for snapshot and time-series simulations with variable load and solar energy to demonstrate equivalent performance of the reduced circuit with the interconnection of PV.

Abstract: Implementations described and claimed herein provide a system and methods for balancing network loads across distinct provider networks. In one implementation, a virtual network representative of at least a first provider network is established having at least one interconnection point where network traffic is exchanged between the first provider network and a second provider network and having at least one provider edge port and at least one potential interconnection point. A measurement of a bandwidth between the at least one provider edge port and the at least one interconnection point is obtained. A measurement of a distance between the at least one provider edge port and a geographically closest of the at least one potential interconnection point or the at least one interconnection point is obtained. A network load indication for the first provider network as a function of the bandwidth measurement and the distance measurement is obtained.

Abstract: Interconnection of one-dimensional nanomaterials such as nanowires and carbon nanotubes with other parts or components is crucial for nanodevices to realize electrical contacts and mechanical fixings. Interconnection has been being gradually paid great attention since it is as significant as nanomaterials properties, and determines nanodevices performance in some cases. This paper provides an overview of recent progress on techniques that are commonly used for one-dimensional interconnection formation. In this review, these techniques could be categorized into two different types: two-step and one-step methods according to their established process. The two-step method is constituted by assembly and pinning processes, while the one-step method is a direct formation process of nano-interconnections. In both methods, the electrodeposition approach is illustrated in detail, and its potential mechanism is emphasized.

Abstract: An interconnection device for elements to be interconnected such as electronic modules or circuits, comprises at least one transmission line coupled to a ground line, the two lines being produced on a face of a dielectric substrate, the interconnection being made substantially at the ends of the transmission line and of the ground line, wherein said interconnection device is flexible over at least a part of its length situated roughly between the elements to be interconnected.

Abstract: Due to the interconnection and active management of Distributed Generation (DG) and Energy Storage Systems (ESSs), the traditional electrical distribution network has become an Active Distribution Network (ADN), posing challenges to the operation optimization of the network. The power supply and storage capacity indexes of a Local Autonomy Control Region (LACR), which consists of DGs, ESSs and the network, are proposed in this paper to quantify the power regulating range of a LACR. DG/ESS and the network are considered as a whole in the model of the indexes, considering both network constraints and power constraints of the DG/ESS. The index quantifies the maximum LACR power supplied to or received from ADN lines. Similarly, power supply and storage capacity indexes of the ADN line are also proposed to quantify the maximum power exchanged between ADN lines. Then a practical algorithm to calculate the indexes is presented, and an operation optimization model is proposed based on the indexes to maximum the economic benefit of DG/ESS. In the optimization model, the power supply reliability of the ADN line is also considered. Finally, the indexes of power supply and storage capacity and the optimization are demonstrated in a case study.

Abstract: This letter reports for the first time the fabrication and characterization of through-silicon vias (TSVs) using air-gap insulators to enable high-performance 3-D integration. To address the challenge in fabricating extremely high-aspect-ratio air gaps, a CMOS-compatible sacrificial technology based on pyrolysis of poly (propylene carbonate) has been developed, upon which air-gap TSVs have been successfully achieved. The measured capacitance density and leakage current density of air-gap TSVs are 1.22 nF/cm2 and 10 nA/cm2, respectively, about one order and two orders lower in magnitude than TSVs using SiO2 insulators.

Abstract: A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.

Abstract: Superconductive interconnection structures providing continuous, uninterrupted superconducting signal paths between a superconducting chip and a superconducting chip carrier are described. The superconductive interconnection structures employ superconducting solder bumps and pillars of Under Bump Metal (“UBM”). The superconductive interconnection structures are employed in a two-stage solder bumping process in which the superconducting chip is first bonded to a testing module for screening and then bonded to a chip packaging module for operation. Either the testing module or the chip packaging module, or both, may include a multi-chip module for carrying multiple superconducting chips simultaneously.

Abstract: A mobile system, including: a 3D device, the 3D device including: a first layer of first transistors, overlaid by at least one interconnection layer, where the interconnection layer comprises copper or aluminum; a second layer including second transistors, the second layer overlaying the interconnection layer, the second layer including: a plurality of electrical connections connecting the second transistors with the interconnection layer; and at least one thermally conductive and electrically non-conductive contact, the at least one thermally conductive and electrically non-conductive contact thermally connects the second layer to the top or bottom surface of the 3D device.

Abstract: An apparatus for applying RF energy to an energy application zone is disclosed. The apparatus may include: a set of receiving radiating elements, including at least first and second radiating elements sequentially interconnected. The sequential interconnection may be such that energy received by one of the receiving radiating element from the energy application zone is emitted back to the energy application zone by the next radiating element in the sequence and energy received by the last radiating element in the sequence from the energy application zone is emitted back to the energy application zone by the first radiating element in the sequence.

Abstract: The augmented cube was introduced as a better interconnection network than the hypercube. An interconnection network needs to have good structural properties beyond simple measures such as connectivity. There are many different measures of structural integrity of interconnection networks. In this paper we prove that if vertices are deleted from an augmented cube of dimension n where g is a quadratic function, the resulting graph will either be connected or will have a large component and small components having at most vertices in total. Additional results on the cyclic vertex-connectivity and the restricted vertex-connectivity of the augmented cubes will also be given.

Abstract: The world's energy paradigm continues to undergo a rapid shift towards an increased use of renewable energy sources. To support this shift, an advanced electric power system architecture is being implemented by many electric utilities, interconnected with new distributed energy resources. As these new installations occur, it is essential to verify that their grid interconnection systems (ICS) conform to the relevant grid interconnection standards and that they perform satisfactorily under a variety of variable resource input and grid output conditions. This paper describes a Grid Interconnection System Evaluator (GISE) that leverages hardware-in-the-loop (HIL) simulation techniques to rapidly evaluate the grid interconnection standard conformance of an ICS according to the procedures in IEEE Std 1547.1TM. The architecture and test sequencing of this evaluation tool, along with a set of representative ICS test results from three different photovoltaic (PV) inverters, are presented. The GISE adds to the National Renewable Energy Laboratory's (NREL) evaluation platform that now allows for rapid development of ICS control algorithms using controller HIL (CHIL) techniques, the ability to test the dc input characteristics of PV-based ICSs through the use of a PV simulator capable of simulating real-world dynamics using power HIL (PHIL), and evaluation of the grid interconnection conformance of an ICS.

Abstract: This paper reports SMT-compatible stress-relief microwire arrays in thin polymer carriers, as a unique, novel and low-cost solution for reliable board-level interconnections between large silicon, glass and low coefficient of thermal expansion (CTE) organic interposers and printed wiring boards. The microwire arrays are pre-fabricated in ultra-thin carriers using low-cost manufacturing processes such as laser vias and copper electroplating, which are then assembled onto the back of the interposer as a stress-relief interlayer. Such a structure is assembled onto the board using standard SMT processes. The microwire array results in dramatic reduction in solder stresses and strains, even with larger interposer sizes (20 mm × 20 mm), at finer pitch (300-400 microns), without the need for underfill. The parallel wire arrays result in low resistance and inductance, and therefore do not degrade the electrical performance. The scalability of the structures and the unique processes, from micro to nanowires, provides extendibility to finer pitch and larger package sizes. The first part of the paper describes the design of microwire array to meet the thermo-mechanical reliability requirements. Finite element method (FEM) was used to study the reliability of the interconnections to provide guidelines for the test vehicle design. Strip models were built to study the reliability of 400 μm-pitch interconnections with a 100 μm thick, 20 mm × 20 mm silicon interposer that was SMT-assembled onto an organic printed wiring board. The performance of the microwire array interconnection is compared with that of ball grid array (BGA) interconnection, in warpage, equivalent plastic strain and projected fatigue life. A unique set of materials and processes was used to demonstrate the low-cost fabrication of the microwire array. Flexible thermoplastic polyimide films were used as the polymer film carriers for the microwire interconnection structure. In the initial feasibility demonstration, 100 μm thick films with laminated copper foil on both sides of the dielectric were used. A 308 nm excimer laser source was used to ablate the via arrays in the polymer. The microwires were batch fabricated by bottom-up electrolytic plating through the polymer template. A low-cost approach to the microwire fabrication is thus demonstrated by partially releasing the wires with controlled etching of the polymer carrier.

Abstract: Provided are a stretchable electronic device and a method of manufacturing the same. The manufacturing method includes forming coil interconnection on a first substrate, forming a first stretchable insulating layer that covers the coil interconnection, forming a second substrate on the first stretchable insulating layer, separating the first substrate from the coiling interconnection and the first stretchable insulating layer, and forming a transistor on the coil interconnection.

Abstract: Metal-interconnected multijunction solar cells offer one pathway toward efficiencies in excess of 50%. However, if a 3- or 4-terminal configuration is used, optical losses from the interfacial grid can be considerable. Here, we examine an alternative which provides an optimal interconnection for two-terminal bonded devices. This “pillar-array” topology is optimized by minimizing the sum of all power losses, including shadow losses and numerically computed electrical losses. Numerical modeling is used to illustrate the benefit of a pillar-array interfacial metallization for some 2-terminal configurations.

Abstract: Provided is an electronic circuit including a substrate having a flat device region and a curved interconnection region. A conduction line may extend along an uneven portion in the interconnection region and may be curved. The uneven portion and the conductive line may have a wavy shape. An external force applied to the electronic circuit may be absorbed by the uneven portion and the conductive line. The electronic device may not be affected by the external force. Therefore, functions of the electronic circuit may be maintained. A method of fabricating an electronic circuit according to the present invention may easily adjust areas and positions of the interconnection region and the device region.

Abstract: The invention discloses a mode control method of an interconnection system and the interconnection system. The mode control method comprises the steps that A. when a mobile terminal is in interconnection with display equipment, the display equipment detects the current working state of the mobile terminal and generates a corresponding mode control indication to be sent to the mobile terminal; B. the mobile terminal is automatically adjusted to be in a preset situational mode matched with the working state of the display equipment according to the mode control indication. When the mobile terminal and the display equipment are in interconnection, the mobile terminal can generate the corresponding mode control indication according to the working state of the display equipment, namely the content played by the display equipment, so that the mobile terminal is controlled and is automatically adjusted to be in the preset situational mode matched with the display equipment, mutual influence of the mobile terminal and the display equipment is avoided when the mobile terminal and the display equipment are used at the same time, automatic matching can be achieved, and a user can carry out controlling conveniently.

Abstract: The selection of a topology is essential to the performance of interconnection networks, so designing a new, cost-effective topology is very significant 2D mesh is one of the most popular topologies However, the diameter and average distance of a 2D mesh are large enough to greatly influence the performance of the network This paper presents a novel topology called TM, which combines the advantages of both a 2D torus and a 2D mesh For an n×n network, the total number of links in a TM is the same as that in a mesh, while the diameter of a TM is extremely close to that of a torus Besides, the average distance of a TM is at the middle of that of a torus and that of a mesh To prevent deadlocks in TMs, a virtual network partitioning scheme is adopted into the TM network Moreover, both of the deterministic and fully-adaptive routing techniques in TMs are proposed in this paper Compared to mesh, the TM network provides average distance and diameter reduction, which contributes to the performance enhancement Sufficient simulation results are presented to show the effectiveness of the TM network, and the new routing schemes proposed for it, by comparing with the mesh network Compared to the torus, which requires at least 3 virtual channels to support fully-adaptive routing, the TM network can support fully-adaptive routing with only 2 virtual channels Seen from the experimental results, in most cases, the performance of TM is worse than the torus, while in some cases, the performance of TM is comparable to torus or even better than the torus

Abstract: The rise of cloud computing and other emerging web applications has increased significantly the network traffic inside the data centers. In this paper we present the future requirements of data centers such as the need for higher bandwidth and the need for more energy-efficient interconnection network inside the data centers. This need comes both from the exponential rise of the network traffic inside the data centers and the limitations of the power consumption in the data center infrastructures. Furthermore, in this paper we discuss the rise of optical interconnection network for data centers that have been proposed in the research literature to address the limitation of the current interconnects. We present the main benefits and drawbacks of each proposed scheme and finally we discuss the research directions in the domain of optical interconnects for data centers.

Abstract: This work aims at answering to the 3D mega trend of silicon based platform and 3D wafer level packaging (3D-WLSiP). We focus on the development of architectures compliant with high volume markets for applications like mobile telecommunication. In this market, the silicon material will remain the key platform for 3D integration and has to offer the vertical interconnection as well as ultra-thin packages to fit into very slim electronic devices. We have designed both a mechanical demonstrator with daisy chains and a fully functional product based on a silicon interposer, focusing on forward and backward compatibility between Front-End and 3D packaging and the development of a complete set of advanced technological modules: - Thru-silicon-via interconnections (TSV) with copper via-mid technologies. - Ultra-thin (20 and 35 μm) chips fabrication using dicing before grinding (DBG) with 45° beveled edge and plasma stress release technology. - Thin chips stack on the TSV interposer before processing the back side (stacking first) with two different approaches. The first one is a flip chip integration based on Cu/SAC μ-bumps while the second is the Back-to-Face (B2F) way based on high topology RDL after permanent bonding of the chips face up on the interposer. Chip bonding is done with several materials either on die side with die attach film (DAF) or on interposer side using wafer level spin coated polymers. - Thin wafer handling using advanced temporary bonding process to handle the thin silicon interposer wafers during the integration based on BSI product from Brewer Science and ZoneBOND™ technology. Moreover different strategies of handling have been investigated involving high topology temporary bonding as well as carrier flip-flop approaches. - Thin wafer level packaging (TWLP) has been implemented sequentially on front side and back side of the thin resulting in a fully 3D-WLSiP module. Thermo-mechanical FEM simulation and first reliability assessment using mechanical demonstrator have been carried out and support the good mechanical behaviour of the integration. Electrical tests have been also completed that allows comparing the performances of F2F and B2F interconnection schemes in terms of resistances and yield at front side level but also at back side level after TSV exposure, RDL and bumps. Successful results of development loops have led to start processing a full functional product benefiting of the best process flow.

Abstract: This paper deals with the canonical interconnection of discrete-time linear port-Hamiltonian systems. A conservative discrete linear port-Hamiltonian dynamics involving a modified conjugate port-output is introduced. It is shown that the projection yielding the discrete dynamics and the composition by canonical interconnection commute. As a by-product, symplecticity of the numerical flow is preserved by interconnection whenever input vector fields are Hamiltonian vector fields, which is analogous to the continuous case. The negative feedback interconnection of two circuits illustrates the results.