Abstract: This paper discusses the optimization of a stretchable electrical interconnection between integrated circuits in terms of stretchability and fatigue lifetime. The interconnection is based on Cu stripes embedded in a polyimide-enhanced (PI-enhanced) layer. Design-of-experiment (DOE) methods and finite-element modeling were used to obtain an optimal design and to define design guidelines, concerning both stripe and layer dimensions and material selection. Stretchable interconnects with a PI-enhanced layer were fabricated based on the optimized design parameters and tested. In situ experimental observations did validate the optimal design. Statistical analysis indicated that the PI width plays the most important role among the different design parameters. By increasing the PI width, the plastic strain in the Cu stripes is reduced, and thus, the stretchability and fatigue lifetime of the system is increased. The experimental results demonstrate that the PI-enhanced stretchable interconnect enables elongations up to 250% without Cu rupture. This maximum elongation is two times larger than the one in samples without PI enhancement . Moreover, the fatigue life at 30% elongation is 470 times higher.

Abstract: There is increasing requests for noncontrollable distribution generation (DG) interconnections in the medium and low voltage networks. Many studies have suggested that with proper system planning, DG could provide benefits such as reliability enhancement, investment deferment, and reduced losses. However, without network reinforcements, the allowable interconnection capacity in a network is often restricted due to fault current level, voltage variation, and power flow constraints. This paper aims to address the issue of optimizing network operation and use for accommodating DG integrations. A new DG interconnection planning study framework that includes a coordinated feeder reconfiguration and voltage control to calculate the maximum allowable DG capacity at a given node in the distribution network is presented. A binary particle swarm optimization (BPSO) technique is employed to solve the discrete nonlinear optimization problem and possible uncertainties associated with volatile renewable DG resource and loads are incorporated through a stochastic simulation approach. Comprehensive case studies are conducted to illustrate the applicability of the proposed method. Numerical examples suggest that the method and procedure used in the current DG interconnection impact study should be modified in order to optimize the existing grid operation and usage to facilitate customer participation in system operation and planning.

Abstract: As the power dissipation of data centers challenges their scalability, architectures for interconnecting computers, or servers must simultaneously achieve high throughput at peak utilization and power consumption proportional to utilization levels. To achieve this goal, this paper proposes the use of an optical multiplane interconnection network, named space-wavelength (SW) switched architecture, able to route and switch packets between servers (on cards) and between processors within a card (or card ports). SW architecture exploits the space domain to address the destination card and the wavelength domain to address the destination port on a per-packet basis. Scalability and energy efficiency of the considered architecture are quantified and compared to typical single-plane architectures. Not only can the SW multiplane architecture achieve higher throughput by exploiting two switching domains, but its performance is shown to be highly scalable with network utilization. More importantly, higher performance is reached with an energy efficiency superior to single-plane architectures. The excellent energy efficiency is achieved using optical devices with low idle power.

Abstract: A low-diameter, fast interconnection network is going to be a prerequisite for building exascale machines. A two-level direct network has been proposed by several groups as a scalable design for future machines. IBM's PERCS topology and the dragonfly network discussed in the DARPA exascale hardware study are examples of this design. The presence of multiple levels in this design leads to hot-spots on a few links when processes are grouped together at the lowest level to minimize total communication volume. This is especially true for communication graphs with a small number of neighbors per task. Routing and mapping choices can impact the communication performance of parallel applications running on a machine with a two-level direct topology. This paper explores intelligent topology aware mappings of different communication patterns to the physical topology to identify cases that minimize link utilization. We also analyze the trade-offs between using direct and indirect routing with different mappings. We use simulations to study communication and overall performance of applications since there are no installations of two-level direct networks yet. This study raises interesting issues regarding the choice of job scheduling, routing and mapping for future machines.

Abstract: A power converter includes a power input configured to receive input power from an AC power source, a power output configured to provide output power to a load, a battery interface configured to exchange DC power with a battery, and power converter circuitry. The power converter circuitry is adapted to, in a first interconnection configuration, convert the input power into the DC power at the battery interface, and, in a second interconnection configuration, convert the DC power at the battery interface into the output power. The power converter circuitry has a power line, a transformer, a first connection node switchably connected to the power line in the first interconnection configuration and switchably connected to the transformer in the second interconnection configuration, and a second connection node switchably connected to the transformer in the first interconnection configuration and switchably connected to the power line in the second interconnection configuration.

Abstract: Smart mobile applications are driving the demand for higher logic-to-memory bandwidth (BW) in 10–30 GB/s range with lower power consumption and larger memory capacity. This paper presents a radically-different, scalable and lower cost approach than the 3D ICs with TSV stack approach being pursued widely, to achieve high bandwidth. This approach is referred to as interposer approach using ultra-thin glass or silicon with ultra-high I/O density interposers, which does not require TSVs in the logic IC in the 3D stack. This paper presents a comparative study, based on electrical modeling of the logic-to-memory signal path, in various current and emerging package configurations for use in smart mobile devices. Frequency and time domain analysis for each of these scenarios is performed using both chip and package-level models with varying interconnection dimensions. Simulated eye diagrams for the complete data paths in the thin glass interposer approach demonstrated more than 3 Gbps/pin data rate, similar to 3D ICs.

Abstract: This paper is devoted on the characterization method of RF/digital PCB interconnections for the prediction of the high- speed signal transient responses. The introduced method is based on the use of the interconnection line RLCG-model. Theoretical formulae enabling the extraction of the electrical per-unit length parameters R, L, C and G in function of the interconnection line physical characteristics (width, length, metal conductivity, dielectric permittivity ...) are established. Then, by considering the second order approximation of the interconnection RLCG-model transfer matrix, the calculation process of the transient responses from the interconnection system transfer function is originally established. To demonstrate the relevance of the proposed model, microwave- digital interconnection structure comprised of millimetre microstrip line driven and loaded by logic gates which are respectively modelled by their input and output impedances was considered. Then, comparisons between the SPICE-computation results and those obtained from the proposed analytical model implemented in Matlab were made. As results, by considering a periodical square microwave-digital excitation signal with 2Gbits/s rate, transient responses which are very well- correlated to the SPICE-results and showing the degradation of the tested signal fldelity are observed. The numerical computations conflrm that the proposed modelling method enables also to evaluate accurately the transient signal parameters as the rise-/fall-times and the 50% propagation delay in very less computation time. For this reason, this analytical-numerical modelling method is potentially interesting for the analysis of the signal integrity which propagates

Abstract: Traditional models for planning interconnection between power systems are mainly concerned with the economic and security benefits. In this paper, the concept of low-carbon economy is introduced into the planning of interconnection while considering the emergence of new factors and their impact on the power system interconnection under the condition of low-carbon economy. The cost of low-carbon power technology and transaction expenses of the carbon trading mechanism involved are incorporated in the objective function, with the reduction targets of CO2 emissions introduced into the constraints. An interconnection planning model is developed with the maximization of the overall interconnection benefit in the planning period under the low-carbon economy as the objective function. A study of the planning of interconnection between two provincial grids in South China shows that the model proposed is effective and practical.

Abstract: Multi-stage Interconnection Networks (MINs) are designed to achieve fault-tolerance and collision solving by providing a set of disjoint paths. Ching-Wen Chen and Chung-Ping Chung had proposed a fault-tolerant network called Combining Switches Multi-stage Interconnection Network (CSMIN) and an inaccurate algorithm that provided two correct disjoint paths only for some source-destination pairs. This paper provides a more comprehensive and accurate algorithm that always generate correct routing-tags for two disjoint paths for every source-destination pair in the CSMIN. The 1-fault tolerant CSMIN causes the two disjoint paths to have regular distances at each stage. Moreover, our algorithm backtracks a packet to the previous stage and takes the other disjoint path in the event of a fault or a collision in the network. Furthermore, to eliminate the backtracking penalties of CSMIN, we propose a new design called Fault-tolerant Fully-Chained Combining Switches Multi-stage Interconnection Network (FCSMIN). It has similar characteristics of 1-fault tolerance and two disjoint paths between any source-destination pair, but it can tolerate only one link or switch fault at each stage without backtracking. Our simulation and comparative analysis result shows that FCSMIN has added advantages of destination-tag routing, lower hardware costs, strong reroutability, lower preprocessing overhead, and higher fault-tolerance power in comparison to CSMIN.

Abstract: The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress and improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21 × 21 mm Cu/low-k test chip on flip chip ball grid array (FCBGA) package. The Cu/low-k chip is a 65-nm nine-metal layer chip with 150-μm SnAg bump pitch of total 11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25 × 25 × 0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45 × 45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free solder bumps and underfill have been set up. The FCBGA samples have passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy chain resistance measurements.

Abstract: According to one embodiment, a graphene interconnection includes an insulating film, a catalyst film, and a graphene layer. An insulating film includes an interconnection trench. A catalyst film is formed in the interconnection trench and filling at least a portion of the interconnection trench. A graphene layer is formed on the catalyst film in the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to a bottom surface of the interconnection trench.

Abstract: This paper presents an energy-efficient multi-plane optical interconnection network to interconnect servers in a data center. The novel architecture uses the time domain to individually address each port within a card and the space domain to address each card. Optical enabling technologies passively time-compress serial packets by exploiting the wavelength domain and perform a broadcast-and-select to a destination card with minimum power dissipation. Scalability of both the physical layer and the overall power dissipation of the architecture is shown to be enhanced with respect to the existing interconnection network architectures based on space and wavelength domains. The space-time network architecture is scalable up to 216 ports with space-switches exhibiting energy efficiency of the order of picojoules per bit, thanks to the self-enabled semiconductor-optical-amplifier-based space-switches.

Abstract: A scalable and reliable architecture for both a wavelength division multiplexing passive optical network and a hybrid wavelength and time division multiplexing passive optical network with self-healing capability is presented and evaluated. Our protection scheme is compatible with a cascaded arrayed waveguide grating that can accommodate an ultra-large number of end users. A simple interconnection pattern between two adjacent optical network units (ONUs) is applied in order to provide protection for distributed fibers between a remote node and the ONUs. Therefore, the investment cost on a per-user basis can be significantly reduced. Meanwhile, the performance evaluation shows that our approach can achieve high connection availability while maintaining the support of long reach and high splitting ratio.

Abstract: This paper presents two complementary techniques to manage the power consumption of large-scale systems with a packet-switched interconnection network. First, we propose Thrifty Interconnection Network (TIN), where the network links are activated and de-activated dynamically with little or no overhead by using inherent system events to timely trigger link activation or de-activation. Second, we propose Network Power Shifting (NPS) that dynamically shifts the power budget between the compute nodes and their corresponding network components. TIN activates and trains the links in the interconnection network, just-in-time before the network communication is about to happen, and thriftily puts them into a low-power mode when communication is finished, hence reducing unnecessary network power consumption. Furthermore, the compute nodes can absorb the extra power budget shifted from its attached network components and increase their processor frequency for higher performance with NPS. Our simulation results on a set of real-world workload traces show that TIN can achieve on average 60% network power reduction, with the support of only one low-power mode. When NPS is enabled, the two together can achieve 12% application performance improvement and 13% overall system energy reduction. Further performance improvement is possible if the compute nodes can speed up more and fully utilize the extra power budget reinvested from the thrifty network with more aggressive cooling support.

Abstract: To propose an appropriate cooling solution for a three-dimensional (3D) chip stack at the design phase, it is necessary to estimate the total thermal resistance of a 3D chip stack. The interconnection between stacked chips is considered as one of the thermal resistance bottleneck of a 3D chip stack, but it is not experimentally clear yet. We have previously measured the thermal conductivity of SnAg with Cu post to be 37–41W/mC by a steady state thermal resistance measurement method, using the sample which was simply composed of two Si chips and SnAg with Cu post between two Si chips. In this study, 3D stacked test chips are fabricated, which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating, and the thermal conductivity of the interconnection in actual 3D stacked structure is experimentally obtained. The temperature distributions of two 3-layer-stacked-test-chips are measured and the equivalent thermal conductivity of the interconnection is experimentally obtained to be 1.6W/mC. This value is compared with the measured thermal conductivity of SnAg with Cu post (37–41W/mC) and its adequacy is examined.

Abstract: According to one embodiment, a semiconductor memory device comprises a first silicon pillar including a first pair of columnar portions and a first connection portion, a second silicon pillar including a second pair of columnar portions and a second connection portion in the shunt region, the second silicon pillar being adjacent to the first silicon pillar, a first interconnection connected to one of the first pair of columnar portions of the first silicon pillar, a second interconnection connected to one of the second pair of columnar portions of the second silicon pillar. The first interconnection is connected to a dummy bit line. The first interconnection and the second interconnection are connected on the same level.

Abstract: Exemplary embodiments of the present techniques provide methods and systems for coarsening a computational mesh, for example, for use in a reservoir simulation. An exemplary method of performing a reservoir simulation, includes generating a data representation in a storage system, wherein the data representation includes an interconnection weight that represents the magnitude of an interconnection between each of a number of computational cells in a computational mesh. A threshold value is compared to each interconnection weight and any interconnection weight that is equal to or less than the threshold value is set to zero.

Abstract: An image sensor package includes an image sensor die having an active side and a backside, wherein an image sensor device region and a bond pad are provided on the active side. A through-silicon-via (TSV) structure extending through the thickness of the image sensor die is provided to electrically connect the bond pad. A multi-layer re-distributed interconnection structure is provided on the backside of the image sensor die. A solder mask or passivation layer covers the multi-layer re-distributed interconnection structure.

Abstract: PoP (Package on Package) structures have been used widely in digital consumer electronics products such as digital still cameras and mobile phones. However, the final stack height from the top to the bottom package for these structures is higher than that of the current stacked die packages. To reduce the height of the package, a flip chip technology is used. Since the logic chips of mobile applications use a pad pitch of less than 80 μm or less, an ultra-fine-pitch flip chip interconnection technique is required. The C4 (Controlled Collapse Chip Connection) flip chip technology is widely used in area array flip chip packages. The C4 was named after the four initial characters which are "C" of Controlled Collapse Chip Connection. The collapse of the molten solder is controlled by the individual opening of solder resist on each pad on the substrate so that the chip can be connected onto the substrate. However, C4 is not suitable in the ultra-fine-pitch flip chips because the such a individual opening which is suitable for the ultra-fine-pitch cannot be made on the substraete. Instead of the C4 flip chip technology, the new interconnection technique was developed using the solder capped Cu pillar bumps. It is very easy to control the space between the die and the substrate by adjusting the Cu pillar height even when a large slit window opening exists on a group of pads on the substrate. Since the collapse control of the solder bumps is not necessary, we call the process C2 (Chip Connection). The C2 was named after the two initial characters which are "C" of Chip Connection. The solder capped Cu pillar bumps are connected to Cu substrate pads, which are a surface treated with OSP (Organic Solder Preservative), by reflow with no-clean processes. This technology creates the SMT (Surface Mount Technology)/flip chip hybrid assembly for SoP (System on Package) use. We have produced 50 μm pitch interconnections and observed the micro structure and tested their reliability. Some voids in the solder joint were observed after the reflow process. The results of warpage measurements and FEM (Finite Element Method) analyses suggest that these voids are the shrinkage voids caused by the wide temperature range of the solder liquid phase and the substrate warpage. Since they are not the stress induced voids, they didn't affect the reliability test. The increase in interconnection resistance during the reliability test was compared between the C2 interconnection and Au stud-solder interconnection. Since the resistance increase of the C2 interconnection is much smaller than that for the Au stud-solder interconnection, it is clear that the C2 flip chip technology provides robust solder connections at low cost. Also the C2 structure with a low-k device was evaluated and no failures were observed at 1,500 cycles in the TC (Thermal Cycle) test. In addition to the fine-pitch interconnections, a die thickness of 70 μm is required to reduce the final stack height. The reliability performance of the C2 flip chip with the die thicknesses 20 μm, 70 μm and 150 μm was also discussed using a PEG (Post-Encapsulation Grinding) method in which the die is ground to less than 70 μm after joining and underfilling. Finally the electromigration tests were performed on the 80 μm pitch C2 interconnection. The tests showed that the solder capped Cu pillar structure has high endurance against electromigration and no failure data was recorded up to 1,000 hrs with several electromigration conditions regardless the direction of electron flow.

Abstract: An apparatus comprises a die comprising a plurality of switch/router circuits; and a plurality of additional dies. Each respective one of the plurality of additional dies comprises: a respective network interface, which is electrically coupled to a respective one of the plurality of switch/router circuits; and a respective interconnection test logic, which is electrically coupled to the respective network interface and the interconnection test logic in at least one other one of the plurality of additional dies.

Abstract: The core of a parallel processing system is the interconnection network by which the system's processors are linked. Due to the great role played by the interconnection network's topology in improving the parallel processing system's performance, various topologies have been proposed in the literature. This paper proposes a new interconnection network topology, referred to as the chained(cubic tree, in which chains of hypercubes are arranged in a tree structure. The major topological properties of the proposed topology have been investigated, including its diameter, degree, connectivity, bisection width, size, cost, and hamiltonicity. A comparative study is then conducted between the proposed CCT and other interconnection networks' topologies, including tree and hypercube in order to evaluate the rank occupied by CCT among other well(known topologies in terms of various performance and cost metrics. The concluding results proved that the CCT topology overcomes the shortcomings of its progenitors, tree and hypercube, while keeping most of its appealing properties.

Abstract: In this paper, we propose a method for interconnecting soft polyimide (PI) electrodes using anisotropic conductive films (ACFs). Reliable and automated bonding was achieved through development of a desktop thermocompressive bonding device that could simultaneously deliver appropriate temperatures and pressures to the interconnection area. The bonding conditions were optimized by changing the bonding temperature and bonding pressure. The electrical properties were characterized by measuring the contact resistance of the ACF bonding area, yielding a measure that was used to optimize the applied pressure and temperature. The optimal conditions consisted of applying a pressure of 4 kgf/cm2 and a temperature of 180 °C for 20 s. Although ACF base bonding is widely used in industry (e.g., liquid crystal display manufacturing), this study constitutes the first trial of a biomedical application. We performed a preliminary in vivo biocompatibility investigation of ACF bonded area. Using the optimized temperature and pressure conditions, we interconnected a 40-channel PI multielectrode device for measuring electroencephalography (EEG) signals from the skulls of mice. The electrical properties of electrode were characterized by measuring the impedance. Finally, EEG signals were measured from the mice skulls using the fabricated devices to investigate suitability for application to biomedical devices.

Abstract: In embodiments of a hinge electrical interconnection guide, a portable device includes a first housing integrated with a display device, and a second housing movably coupled to the first housing. A hinge assembly includes a hinge link to couple hinge mechanisms that are movably operable to open and close the first and second housings of the portable device relative to each other. An electrical interconnection guide is integrated with the hinge link and designed to route an electrical interconnection in a first configuration between the first and second housings of the device when closed relative to each other. The electrical interconnection guide is also designed to route the electrical interconnection in a second configuration between the first and second housings of the device when open relative to each other.

Abstract: A reliable, energy-efficient on-chip interconnection network employing low-swing signaling can be designed by incorporating error-correcting code. Orthogonal Latin Square Code (OLSC) can protect the interconnection against transient errors, while also lowering energy consumption. When applied to a 64-bit link using a 45-nm CMOS technology with low-swing signaling, OLSC provided up to 55% energy reduction, with only a small area overhead and no loss in reliability.

Abstract: 3D integration requires a physical stacking of die/wafer onto another die/wafer while forming a permanent electrical and mechanical connection between the input/output pins of the devices. Tin-based micro-bump (μbump) connections using copper (Cu) or nickel (Ni) Under-Bump-Metallurgy (UBM) with interconnect pitches of 40 μm and smaller are generally considered to be the leading candidates for these high density Si-to-Si interconnects, particularly because of their tolerance to height variation, similarity to standard flip-chip solder joints and ease of processing. In this paper, a systematic study of the metallurgical interactions in the Ni/Cu/Sn system is presented, using both stacks of blanket films and μbumps. Furthermore, a novel Ni/Cu/Sn μbump scheme is developed to replace the conventional Cu/Ni/Sn or Cu/Sn schemes in order to improve the μbump solder joint quality and reliability. Here a very thin layer of Cu between Ni UBM and Sn solder is used to avoid the formation of (Ni, Cu) 3 Sn or Cu 3 Sn and significantly reduce void formation.

Abstract: In the era of the nanometer CMOS technology, due to stringent system requirements in power and performance, microprocessor manufacturers are relying more on chip multi-processor (CMP) designs. CMPs partition silicon real estate among a number of processor cores and on-chip caches, and these components are connected via an on-chip interconnection network (Network-on-chip). It is projected that communication via NoC is one of the primary limiters to both performance and power consumption. To mitigate such problems, we explore the use of multiband RF-interconnect (RF-I) which can communicate simultaneously through multiple frequency bands with low power signal transmission and reconfigurable bandwidth. At the same time, we investigate the CMOS mixed-signal circuit implementation challenges for improving the RF-I signaling integrity and efficiency. Furthermore, we propose a micro-architectural framework that can be used to facilitate the exploration of scalable low power NoC architectures based on physical planning and prototyping.

Abstract: The present invention relates to a composite assembly of plastic (1, 3) and metal films (2.1, 2.2) which can be used for the interconnection and connection of light-emitting diodes (LEDs) (5). For this purpose, a flexible printed circuit board is provided, to which at least one radiation source is applied and which consists of a film system. The flexible printed circuit board has a thermal connection (6) to a heat sink (4) and the film system is composed at least of an insulating carrier layer and a metal film. The insulating carrier layer is opened at the locations at which the thermal connection to the heat sink is produced, and the metal film is subdivided into different sections.