Abstract: Three-dimensional (3D) chip integration may provide a path to miniaturization, high bandwidth, low power, high performance and system scaling. Integration options can leverage stacked die and/or silicon packages depending on applications. The enabling technology elements include: (i) through-silicon-vias (TSV) with thinned silicon wafers, (ii) fine pitch wiring, (iii) fine pitch interconnection between stacked die, (iv) fine pitch test for known-good die, and (v) power delivery, distribution and thermal cooling technology. Applications may range from miniaturization of portable electronics like image sensors and cell phones to power efficient, high performance computing solutions such as servers and super computers. Silicon based packaging and 3D stacked die technologies have been in research studies for more than a decade at IBM and in industry, universities & consortia. IBM research experiments have included test vehicle design, build, characterization and modeling. Robust structures and processes have been developed based on (i) process learning for silicon based structures, (ii) assembly process comparisons for fine pitch chip interconnection, (iii) electrical, mechanical and thermal characterization and (iv) reliability & accelerated stress characterization. TSV technology investigations have included composite, copper and tungsten metallurgies. Wiring demonstrations ranged from sub-micron fine pitch wiring line widths & spaces to larger dimensions. I/O interconnections investigated feature sizes such as 100 I/O / mm2, 400 I/O/mm2, and interconnection features sizes which support 2500 I/O / mm2. In addition, integrated decoupling capacitors of one hundred ten nano-farads per mm2 per layer and assembly of module structures on silicon packages with ceramic or organic base packages were demonstrated. Examples of robust TSV structures and characterization, single die with silicon interposers, multiple die on a silicon package and stacked die assemblies are given along with highlights of characterization including aspects of electrical, mechanical and reliability results. This research paper describes recent advances in industry and reports advancements from IBM in the design, technical challenges and progress toward 3D chip integration structures. In addition, examples of potential applications that may take advantage of 3D integration are discussed.

Abstract: A method of fabricating a metal interconnection and a method of fabricating image sensor using the same are provided. The method of fabricating a metal interconnection including forming a interlayer dielectric layer on a substrate, forming an interconnection formation region in the interlayer dielectric layer, performing an ultraviolet (UV) treatment on the substrate after the interconnection formation region is formed and forming a metal interconnection in the interconnection formation region.

Abstract: As traditional CMOS scaling becomes progressively more difficult and less beneficial to overall system performance, three-dimensional silicon integration technologies have begun to receive considerable attention. An advanced packaging solution based on a thin silicon carrier has been developed to provide interconnection between integrated circuits (ICs) and other devices at densities. far beyond those of current first-level packaging. The silicon carrier employs fine-pitch Cu damascene wiring, high-density solder interconnections, and through-silicon vias (TSVs). A key enabling technology element is the TSV, which may be naturally scaled to provide vertical interconnection in stacked ICs as well as silicon carriers. In this paper, we discuss the evolution in both TSV design and process flow that has led to TSV technology which produces vias with resistances on the order of 10-20 mΩ and yields on the order of 99.99% at wafer level in a research laboratory environment. Two generalized process approaches to forming TSVs are discussed, the "vias-first" and the "vias-last" methods, along with related advantages and potential drawbacks of each. Improvement to these process, flows and structures is afforded by simple changes of via geometry from cylindrical to annular or from annular to multibar. While various TSV metallurgies are reviewed, tungsten is shown to be a nearly optimal choice. Results on via resistance, electrical yield, and current-carrying capacity are covered. The use of electrical modeling to predict structures with superior electrical and mechanical properties is also described.

Abstract: Interconnects play an increasingly important role in determining the power and performance characteristics of modern processors. an enhanced version of the popular CACTI tool primarily focuses on interconnect design for large scalable caches. the new version can help evaluate novel interconnection networks for cache access and accurately estimate the delay, power, and area of large caches with uniform and nonuniform access times.

Abstract: A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. An extension network connects input/output ports of the interconnection network to input/output ports of one or more peripheral devices, each input/output port of the interconnection network being associated with one of the processor tiles such that each input/output port of the interconnection network sends input data to the corresponding processor tile and receives output data from the corresponding processor tile. The extension network is configurable such that a mapping between input/output ports of the interconnection network and input/output ports of the one or more peripheral devices is configurable.

Abstract: Motivations for three-dimensional (3D) integration include reduction in system size, interconnect delay, power dissipation and enabling hyper-integration of chips fabricated using disparate process technologies. Although various low-power commercial products exploit the advantages of improved performance and increased device packing density realized by 3D stacking of chips (using wirebonds), such technologies are not suitable for high-performance chips due to ineffective power delivery and heat removal. This is important because high performance chips are projected to dissipate more than 100 W/cm2 and require more than 100 A of supply current. Consequently, when such chips are stacked, the challenges in power delivery and cooling become greatly exacerbated. Thus, revolutionary interconnection and packaging technologies will be needed to address these limits [Bakir, et. al., (2007)]. This paper reports, for the first time, the configuration, fabrication, and experimental results of a 3D integration platform that can support the power delivery, signaling, and heat removal requirements for high-performance chips. The key behind this 3D platform is the ability to process integrate, at the wafer-level, electrical and microfluidic interconnection networks on the wafer containing the electrical circuitry and assemble such chips using conventional flip-chip technology.

Abstract: Portable electronic products demand multifunctional module comprising digital, RF and memory functions. Through-silicon via technology provides a means of implementing complex, multi-functional integration with a higher packing density for a System in Package. A 3D silicon module with through silicon via has been developed in this work. Thermo-mechanical analysis has been performed and through silicon via interconnect design is optimized. Multiple chips representing different functional circuits are assembled using wirebond and flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the burrier copper via is exposed by special backgrinding process. A two-stack silicon module is developed and characterized in this work. Power distribution design for the silicon carrier suitable for 5 GHz digital application is studied and characterized. The module reliability has been evaluated under temperature cycling (- 40/125degC) and drop test. Samples with over-mold and underfill passed the JEDEC drop test of 1500 G & 0.5 ms pulse duration. Thermal cycle test results showed no solder joint failure.

Abstract: A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang.

Abstract: This paper proposes a novel on-chip interconnection network adapted to a flexible multiprocessor LDPC decoder based on the de Bruijn network. The main characteristics of this network - including its logarithmic diameter, scalable aggregate bandwidth, and optimized routing technique- allow it to efficiently support the communication intensive nature of the application. We present a detailed hardware implementation of the routers and the network interfaces as well as the packet format and the routing algorithm. The latter is a parallelized version of the shortest path with deflection routing algorithm. In order to evaluate the performance of the proposed network, a generic RTL VHDL description has been developed and synthesized with CMOS STMicroelectronics 0.18 mum technology. The flexibility and the scalability of this on-chip communication network enable it to be used for any kind of LDPC code.

Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

Abstract: A crucial challenge in packaging of microsystems is microfluidic interconnections. These have to seal the ports of the system, and have to provide the appropriate interface to other devices or the external environment. Integrated fluidic interconnections appear to be a good solution for interconnecting polymer microsystems in terms of cost, space and performance. Following this path we propose a new reversible, integrated fluidic interconnection composed of custom-made cylindrical rings integrated in a polymer house next to the fluidic network. This allows plug‘n’play functionality between external metal ferrules and the system. Theoretical calculations are made to dimension and model the integrated fluidic interconnection. Leakage tests are performed on the interconnections, in order to experimentally confirm the model, and detect its limits.

Abstract: A parallel optical transceiver module with 24-transmitter plus 24-receiver channels has been designed and fabricated. The transceiver Optochip relies on silicon carrier technology to provide a high level of integration of the electrical and optical components onto a single substrate with high density interconnection. The transceiver Optochip consists of the Si carrier platform with 4 flip-chip attached components: two 24-channel 850 nm optoelectronic arrays (VCSELs and photodiodes) and two 24-channel CMOS ICs (receivers and laser drivers). Furthermore, 150-mum diameter "optical vias" are incorporated in the Si carrier at 48 locations of the VCSEL and PD array element in order to allow optical transmission through the silicon carrier. A lens arrays aligned to the optical vias can also be integrated into the Si carrier to collimate the optical inputs/outputs and facilitate optical coupling to/from the Optochip. Complete Optochips have been assembled and fully characterized using optical coupling into multimode fiber (MMF) with all channels fully operational. The 24 transmitter channels showed good performance up to 15 Gb/s with uniform, high optical output power and low jitter. The 24 receiver channels, characterized as full Tx-to-Rx Optochip links, operated error-free up to 12.5 Gb/s. At 12.5 Gb/s, each complete link consumes only 11 mW/Gb/s. The Optochip achieves a 300 Gb/s bidirectional data rate, a new record for parallel optical transceivers.

Abstract: Three-dimensional (3D) integration technology promises to continue enhancing integrated-circuit system performance with high bandwidth, low latency, low power, and a small form factor for a variety of applications. In this work, conventional C4 (controlled-collapse chip connection) technology is studied for robust interconnection between stacked thin chips. Various solder hierarchies to enable 3D chip stacking and packaging are investigated. Examples are presented to compare stacking schemes with sequential and parallel reflow. Chips as thin as 90 µm are stacked using conventional chip-placement and reflow processes, and the associated process challenges are investigated and discussed. Warpage of the thin chips is measured on various substrates. Rework of the chip stack has also been demonstrated through a temporary chip attachment operation, and the scalability of reworkable C4 is investigated.

Abstract: As the number of cores on a chip increases, power consumed by the communication structures takes a significant portion of the overall power budget Many application-specific systems on chips (SoCs) involve heterogeneous cores with varied functionality and communication requirements, such as those in mobile-phone systems If a regular network-on-chip is designed to fit the requirements of few high-communicative components, it will be largely over-designed with respect to the needs of the remaining components Consequently, irregular network architectures might be necessary for realising application-specific SoCs The authors propose a power-aware topology construction method, which can construct application-specific low-power interconnection topologies according to the traffic characteristics of SoCs They take several multimedia applications as case studies and experimental results show the power savings of power-aware topology approximate to 49% of the interconnection architecture They also implement a simulator to experiment more general large scale systems, and the results show that customised irregular networks are clearly superior to traditional regular architectures in terms of performance and energy

Abstract: In current reconfigurable architectures, the interconnection structures increasingly contribute more to the delay and power consumption. The demand for increased clock frequencies and logic density (smaller area footprint) makes the problem even more important. Three-dimensional (3D) architectures are able to alleviate this problem by accommodating a number of functional layers, each of which might be fabricated in different technology. However, the benefits of such integration technology have not been sufficiently explored yet. In this paper, we propose a software-supported methodology for exploring and evaluating alternative interconnection schemes for 3D FPGAs. In order to support the proposed methodology, three new CAD tools were developed (part of the 3D MEANDER Design Framework). During our exploration, we study the impact of vertical interconnection between functional layers in a number of design parameters. More specifically, the average gains in operation frequency, power consumption, and wirelength are 35%, 32%, and 13%, respectively, compared to existing 2D FPGAs with identical logic resources. Also, we achieve higher utilization ratio for the vertical interconnections compared to existing approaches by 8% for designing 3D FPGAs, leading to cheaper and more reliable devices.

Abstract: A battery cell interconnect and voltage sensing assembly and a method for coupling a battery cell assembly thereto are provided. The battery cell interconnect and voltage sensing assembly includes a circuit board, electrical interconnect members, and an electrical connector. The circuit board further has slots therethrough for receiving the electrical interconnect members thereon. Electrical terminals from battery cell assemblies are coupled to the electrical interconnect members. The circuit board also has electrical traces for routing voltages at the electrical interconnect members to the electrical connector for sensing voltages of the battery cell assemblies.

Abstract: Over the past 40 years, higher computing power was achieved primarily through commensurate performance enhancement of transistors by continuously scaling down the device dimensions as described by Moore’s Law. Integrated circuits (ICs) have essentially remained a planar platform throughout this period of rigorous scaling. As performance enhancement through device scaling becomes more challenging and demand for higher functionality increases, there is tremendous potential to explore the third dimension, i.e., the vertical dimension of ICs. This was rightly envisioned and pointed out by Richard Fenyman, physicist and Nobel Laureate, when he delivered a talk on “Computing Machines in the Future” in Japan in 1985; his original text reads: “Another direction of improvement (of computing power) is to make physical machines three dimensional instead of all on a surface of a chip. That can be done in stages instead of all at once – you can have several layers and then add many more layers as time goes on” [1]. While dimensional scaling has consistently improved device performance in terms of gate switching delay, it has a reverse effect on global interconnect latency [2]. The global interconnect resistance–capacitance (RC) delay has increasingly become the circuit performance limiting factor especially in the deep submicron regime. Even though Cu/lowmultilevel interconnect structures improve interconnect RC delay, they are not a long-term solution since the diffusion barrier required with Cu metallization has a finite thickness that is not readily scaled. The effective resistance of the interconnect is larger than that would be achieved with bulk Cu, and the difference increases with reduced interconnect width. Surface electron scattering further increases the Cu line resistance, and hence the RC delay suffers [3]. When chip size continues to increase to accommodate more functionality, the total interconnect length increases at the same time. This causes a tremendous amount of power to be dissipated unnecessarily in the interconnect and in repeaters

Abstract: A method of forming contacts for an interconnection element (10), includes (a) joining a conductive element (16) to an interconnection element 10 having multiple wiring layers, (b) patterning the conductive element (16) to form conductive pins (20), and (c) electrically interconnecting the conductive pins (20) with conductive features of the interconnection element (10). A multiple wiring layer interconnection element (10) having an exposed pin interface, includes an interconnection element (10) having multiple wiring layers separated by at least one dielectric layer (24), the wiring layers including a plurality of conductive features exposed at a first face of the interconnection element (10), a plurality of conductive pins (20) protruding in a direction away from the first face, and metal features (22) electrically interconnecting the conductive features with the conductive pins (20).

Abstract: In deep submicron (DSM) VLSI technologies, it is becoming increasingly harder for a copper based electrical interconnect fabric to satisfy the multiple design requirements of delay, power, bandwidth, and delay uncertainty. This is because electrical interconnects are becoming increasingly susceptible to parasitic resistance and capacitance with shrinking process technology and rising clock frequencies, which poses serious challenges for interconnect delay, power dissipation and reliability. On-chip communication architectures such as buses and networks-on-chip (NoC) that are used to enable inter-component communication in multi-processor systems-on-chip (MPSoC) designs rely on these electrical interconnects at the physical level, and are consequently faced with the entire gamut of challenges and drawbacks that plague copper-based electrical interconnects. To overcome the limitations of traditional copper-based electrical interconnects, several research efforts have begun looking at novel interconnect alternatives, such as on-chip optical interconnects, wireless interconnects and carbon nanotube-based interconnects. This paper presents an overview and current state of research for these three promising interconnect technologies. We also discuss the existing challenges for each of these technologies that remain to be resolved before they can be adopted as replacements for copper-based electrical interconnects in the future.

Abstract: We propose a flexible opto-electronic circuit board (FOECB) for in-device interconnection, which is combined with a flexible printed circuit (FPC) with flexible optical waveguides having 45deg mirrors for 90deg beam turning using adhesive film. The fabricated prototype shows total optical loss of 3.7 dB, and the prototype, which mounted a 4-ch vertical-cavity surface-emitting laser (VCSEL) array and a 4-ch photodiode (PD) array, successfully demonstrated optical signal transmission at a data rate of 10 Gbps/ch. These results show that the proposed prototype has considerable potential to realize practical FOECB for in-device interconnection.

Abstract: A top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed. The top-side cooled compact semiconductor package includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous elevation-adaptive interconnection plates for bonding and interconnecting top contact areas of the semiconductor dies with the circuit substrate, a first member of the elevation-adaptive interconnection plates has a first flat-top area and a second member of the elevation-adaptive interconnection plates has a second flat-top area in level with the first flat-top area, a bypass capacitor, having two capacitor terminals located at its ends, stacked atop the two interconnection plate members while being bonded thereto via the first flat-top area and the second flat-top area for a reduced interconnection parasitic impedance.

Abstract: Interconnection of back contact photovoltaic cells in a photovoltaic module is described. Pre-assembled busbars are connected with a configuration to enable correction for cell misalignment in the module.

Abstract: Demand for high speed, high density, small size, and multifunctional electronic devices has driven the development of 3D integration. Both die-to-die-stack and package-on-package 3D integration are in mass production. However, through silicon via (TSV) 3D integration is the future direction. Materials and processes for TSV 3D interconnection are reviewed in this paper. Those include processes for via drilling process, via liner (insulating) material, and via filling material. The materials for thin wafer support, mechanical, and electrical interconnection for TSV devices are also discussed.

Abstract: A novel protection architecture for passive optical networks (PONs) is presented and evaluated. It is based on the cyclic property of arrayed waveguide gratings (AWGs) and the interconnection between two adjacent optical network units. The proposed scheme is compatible with both wavelength-division-multiplexing (WDM) PONs and hybrid WDM/time-division-multiplexing PONs. It is compared with two existing schemes and shown to have several advantages: 1) 50% less wavelengths is needed; 2) the fiber interconnections are simplified; 3) the connection availability is improved by one order of magnitude.

Abstract: PROBLEM TO BE SOLVED: To provide a method for vertical interconnection of 3D electronic modules using a via. SOLUTION: This invention relates to the method for vertical interconnection of the 3D electronic modules using the via, wherein one module includes a laminate which has K electronic wafer levels 19 electrically connected each other by a conductor extending along the laminate. The method includes the steps of: (a) providing at least one electronic component which is surrounded with insulated resin and connected to an electric connection pad, wherein the pad is connected to an electric connection track deposited on a dielectric layer, and each track extends to an electrode located in a position where the via 15 will be formed on a dicing line; (b) laminating and assembling the K wafer levels; (c) forming via vertically in resin; (d) performing metallization of the wall of the via by electrolytic growing; and (e) cutting the laminate along with the dicing line so that the 3D electronic module may be obtained. COPYRIGHT: (C)2009,JPO&INPIT

Abstract: The purpose of this paper was to investigate the effect of thermal cycling on the high-frequency behavior of ball grid array (BGA) interconnection structures. In order to characterize the applicability of RF measurements in predicting interconnection breakdown, a broadband BGA transition structure between a radio frequency printed wiring board (RF-PWB) and a ceramic module was fabricated. In addition to basic assemblies consisting of two BGA transitions between the module and substrate, the designed transition was applied in a passband filter module to demonstrate the effect of thermal cycling on the performance of a practical device, as well. The BGA test modules mounted on the PWBs were exposed to thermal cycling testing over a temperature range of -40degC to + 125degC. To detect interconnection failures induced by cyclic thermal stresses, both dc resistance and scattering parameter measurements were performed on the test assemblies at specific intervals. Parallel to the electrical measurements, crack propagation in the vicinity of the BGA transition structure was investigated using scanning acoustic microscopy (SAM). Moreover, scanning electron microscopy (SEM) was used to determine the failure mechanisms of the test assemblies. Degradation of the signal transmission characteristics of the basic assemblies was first observed at higher microwave frequencies as an increase in signal return loss (|S11|) and/or a change in its phase. The effect of TCT on the filter assembly was more constant and clearer to observe in the phase than in the magnitude of S11 in the passband. The dc resistance measurements showed no indication of degradation in any of the tested assemblies.

Abstract: A direct galvanic connection between a cable, having a preferred flat cross-section, and an electronic Printed Circuit Board (“Target PCB”) ( 228 ) by means of an intermediate PCB (“Interconnection PCB”) ( 200 ) allowing an impedance matched and length balanced electrical connection is described, thus offering ideal conditions for high speed and high frequency data connections At the same time, the invention allows to keep the flexibility of a modular production and assembly workflow, typical of the use of well known connectors