Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which can increase contact reliability between a through interconnection line and each pad and thereby improve the yield of a chip, and also to provide its manufacturing method. SOLUTION: Inside a through hole 2 penetrated in the thickness direction of a semiconductor substrate 1, the through interconnection line 4 made of a metal (such as copper and nickel) is formed via an insulation film 3. On both end faces in the longitudinal direction of the through interconnection line 4, the pads 5 and 6 are stacked. The insulation film 3 is formed not only on the inner surface of the through hole 2 of the semiconductor substrate 1 but also on both faces in the thickness direction of the semiconductor substrate 1. On both faces of the semiconductor substrate 1, the pads 5 and 6 are so formed as to be extended over the end face of the through interconnection line 4 and the surface of the insulation film 3. The through hole 2 is formed in such a shape that the opening areas may become larger as they come closer to one and the other face sides of the semiconductor substrate 1. COPYRIGHT: (C)2007,JPO&INPIT

Abstract: The TRIPS chip prototypes two networks on chip to demonstrate the viability of a routed interconnection fabric for memory and operand traffic. In a 170-million-transistor custom ASIC chip, these NoCs provide system performance within 28 percent of ideal noncontended networks at a cost of 20 percent of the die area. our experience shows that NoCs are area- and complexity-efficient means of providing high-bandwidth, low-latency on-chip communication.

Abstract: A wireless interconnection scheme based on capacitive coupling provides mono- and bi-directional transmission capabilities for 3-D system integration. Chips are implemented in 0.13 mum CMOS technology and assembled face-to-face at die-level. RX-TX circuits are specifically designed for low-power functionality and the implementation takes advantage of the two different voltage thresholds that are available for the standard transistors in the CMOS process we used. The communication circuits are coupled via electrodes with an area down to 8 times 8 mum2 and this enables the vertical propagation of clock signals at 1.7 GHz, a propagation delay of 420 ps for general purpose signals and a throughput of more than 22 Mb/s/mum2 with 0.08 pJ/b energy consumption.

Abstract: With small dimensional optics, small photovoltaic cells have heat distribution surfaces, very high concentrations and subsequently high utilization of the semiconductors can be achieved. Discrete photodiodes can be formed as spherical and other geometric shaped, cells with high performance characteristics, precision dimensions, and low cost. This invention positions discrete photovoltaic cells by using their geometric shape, elastic electrical mounts, couples them to small optical concentrator systems of refractory and or reflective optics and makes electrical network connections to those photodiodes, reliably, adjusting for thermal expansion, and at low cost to form low cost and reliable electrical power arrays. The electrical connectors and network can form part of the reflective optics and heat removal system. The electrical interconnection system can also form a reliable network that is self-correcting and tolerant of point failures.

Abstract: Ultralow-latency interconnection networks have become a necessity in modern high-performance computing systems. recent advances in photonic integration technology are paving the way for a disruptive step in the design of these networks. We present SPINet, an optical interconnection network architecture designed for implementation using photonic integration, providing an end-to-end photonic path while completely avoiding optical buffering. SPINet resolves contentions through message dropping, but facilitates message recovery using a novel physical-layer acknowledgment protocol.

Abstract: This paper presents efficient mechanisms for delay- sensitive transmission of video over IEEE 802.11a/e wireless local area networks (WLANs). Transmitting video over WLANs in real time is very challenging due to the time-varying wireless channel and video content characteristics. This paper provides a comprehensive view of how to adapt the quality of service signaling, IEEE 802.11e parameters and cross-layer design to optimize the video quality at the receiver. We propose an integrated system view of admission control and scheduling for both contention and poll-based access of IEEE 802.11e medium access control (MAC) protocol and outline the merits of each approach for video transmission. We also show the benefits of using a cross-layer optimization by sharing the application, MAC, and physical layer parameters of the open systems interconnection stack to enhance the video quality. We will show through analysis and simulation that controlling the contention-based access in IEEE 802.11e is simple to realize in real products and how different cross-layer strategies used in poll-based access lead to a larger number of stations being simultaneously admitted and/or a higher video quality for the admitted stations. Finally, we introduce a new concept called time fairness, which is critical in enhancing the video performance when different transmitter-receiver pairs deploy different cross-layer strategies.

Abstract: A wiring substrate includes a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via hole formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film, the second interconnection being connected to the first interconnection via the via conductor. The wiring substrate includes divided-substrate-unit regions, in each of which the first interconnection, the via conductor, and the second interconnection are formed. The wiring substrate includes a warpage-controlling pattern on the base insulating film, and has a warped shape such that when the wiring substrate is left at rest on a horizontal plate, at least a central part of each side of a plane surface of the substrate contacts the horizontal plate, with both ends of the side raised, where each of the sides extends along a second direction perpendicular to a first direction in the plane surface of the substrate.

Abstract: All optical path interconnection networks employing dense wavelength division multiplexing can provide vast improvements in supercomputer performance. However, the lack of efficient optical buffering requires investigation of new topologies and routing techniques. This paper introduces and evaluates the data vortex optical switching architecture which uses cylindrical routing paths as a packet buffering alternative. In addition, the impact of the number of angles on the overall network performance is studied through simulation. Using optimal topology configurations, the data vortex is compared to two existing switching architectures-butterfly and omega networks. The three networks are compared in terms of throughput, accepted traffic ratio, and average packet latency. The data vortex is shown to exhibit comparable latency and a higher acceptance rate (2times at 50 percent load) than the butterfly and omega topologies

Abstract: Interconnection networks have been deployed as the communication fabric in a wide spectrum of parallel computer systems, ranging from chip multiprocessors (CMPs) and embedded multicore systems-on-a-chip (SoCs) to clusters and server blades. Recent technology trends have permitted a rapid growth of chip resources, faster clock rates, and wider communication bandwidths, however, these trends have also led to an increase in power consumption that is becoming a key limiting factor in the design of such scalable interconnected systems. Power-aware networks, therefore, need to become inherent components of single and multi-chip parallel systems. In the hardware arena, recent interconnection network power-management research work has employed limited-scope techniques that mostly focus on reducing the power consumed by the network communication links. As these limited-scope techniques are not tailored to the applications running on the network, power savings and the corresponding impact on network latency vary significantly from one application to the next as we demonstrate in this paper; in many cases, network performance can severely suffer. In the software arena, extensive research on compile-time optimizations has produced parallelizing compilers that can efficiently map an application onto hardware for high performance. However, research into power-aware parallelizing compilers is in its infancy. In this paper, we take the first steps toward tailoring applications' communication needs at run-time for low power. We propose software techniques that extend the flow of a parallelizing compiler in order to direct run-time network power reduction. We target network links, a significant power consumer in these systems, allowing dynamic voltage scaling (DVS) instructions extracted during static compilation to orchestrate link voltage and frequency transitions for power savings during application run-time. Concurrently, an online hardware mechanism measures network congestion levels and adapts these off-line DVS settings to maximize network performance. Our simulations over three existing parallel systems, ranging from very fine-grained single-chip to coarse-grained multi-chip architectures, show that link power consumption can be reduced by up to 76.3p, with a minor increase in latency, ranging from 0.18 to 6.78p across a number of benchmark suites.

Abstract: This paper presents a 3D interconnection scheme based on capacitive coupling. We propose synchronous communication circuits, based on a precharge and transmission approach, that provide an optimization of interconnection sensitivity. Measurements on a 0.13 ?m CMOS implementation demonstrate working connections with an area occupation of 8 × 8 ?m2 . Experimental results are presented for both die-to-die and wafer-to-wafer assembly techniques. They show a maximum communication bandwidth of 1.23 Gb/s, leading to a throughput per area of 19 Mb/s/?M2 with an energy consumption of 0.14 mW/Gb/s. BER measurements demonstrate the reliability of these AC interconnections with no error on more than transmitted.

Abstract: There is provided a solar cell array and a solar cell module including the solar cell array, comprising: a solar cell wafer (10) including a semiconductor substrate (1) and a p electrode (11) and an n electrode (12) provided at a surface of the semiconductor substrate (1); an interconnection substrate (38) including an insulating substrate (36) having a light receiving surface and a p interconnection (34) and an n interconnection (35) provided at the light receiving surface and electrically insulated from each other, on the interconnection substrate (38), more than one solar cell wafer (10) being disposed adjacently, the p electrode (11) and the p interconnection (34) being electrically connected, the n electrode (12) and the n interconnection (35) being electrically connected; and an interconnection (32) formed such that the p interconnection (34) electrically connected to one solar cell wafer (10) and the n interconnection (35) electrically connected to another solar cell wafer (10) adjacent to one solar cell wafer (10) are electrically connected at the light receiving surface and a surface opposite thereto.

Abstract: Methods and apparatuses for an electronic assembly. The electronic assembly has a first object created and separated from a host substrate. The first object has a first electrical circuitry therein. A carrier substrate is coupled to the first object wherein the first object is being recessed below a surface of the carrier substrate. The carrier substrate further includes a first carrier connection pad and a second carrier connection pad that interconnect with the first object using metal connectors. A receiving substrate, which is substantially planar, including a second electrical circuitry, a first receiving connection pad, and a second receiving connection pad that interconnect with the second electrical circuitry using the metal connectors. The carrier substrate is coupled to the receiving substrate using the connection pads mentioned.

Abstract: A system is presented providing content to a plurality of handheld devices (including musical selections). The devices can access a server over the Internet via a Wi-Fi or other similar wireless interconnection and can download songs requested by a user from the server or from other users using, e.g., a P2P protocol. All downloads may be governed by applicable DRM rules. Content and playlists may also be pushed by a server from other sources and means including, e.g., podcasting, based on predetermined rules, favorite preferences of users, and other criteria.

Abstract: Thermal protection is provided in systems utilizing high-current double-layer capacitors. For example, in one implementation, an interconnection coupled to at least one double-layer capacitor that carries capacitor current to or from the at least one double-layer capacitor is functionally coupled to the at least one double-layer capacitor to reduce a temperature of the capacitor is provided.

Abstract: In accordance with the present invention, during formation of the interconnection board, the interconnection board remains securely fixed to a high rigidity plate being higher in rigidity than the interconnection board for suppressing the interconnection board from being bent.

Abstract: In the present invention, copper interconnection with metal caps is extended to the post-passivation interconnection process. Metal caps may be aluminum. A gold pad may be formed on the metal caps to allow wire bonding and testing applications. Various post-passivation passive components may be formed on the integrated circuit and connected via the metal caps.

Abstract: This paper starts with the two-stage Voltage-Regulator (VR) solution for future server microprocessors. By using two-stage solution, high efficiency and high power density VR can be put as close as the microprocessor to eliminate the interconnection effect. Then, high efficiency high power density voltage divider which is served as the 1st stage is analyzed and optimal design is illustrated. Finally, a 2500 W/in3 interleaved voltage divider with 97~98% efficiency is experimentally verified.

Abstract: A modular photonic interconnection network based on a combination of basic 2times2 all-optical nodes including a photonic combinatorial network for the packet contention management is presented. The proposed architecture is synchronous, can handle optical time division multiplexed (OTDM) packets up to 160 Gb/s, exhibits self-routing capability, and very low switching latency. In such a scenario, OTDM has to be preferred to wavelength division multiplexing (WDM) because in the former case, the instantaneous packet power carries the information related to only one bit, making the signal processing based on instantaneous nonlinear interactions between packets and control signals more efficient. Moreover, OTDM can be used in interconnection networks without caring about the propagation impairments because of the very short length (<100 m) of the links in these networks. For such short-range networks, the packet synchronization can be solved at the network boundary in the electronic domain without the need of complex optical synchronizers. In this paper, we focus on a photonic combinatorial network able to detect the contentions, and to optically drive the contention resolution block and the switching control block. The implementation of the photonic combinatorial network is based on semiconductor devices, which makes the solution very promising in terms of compactness, stability, and power consumption. This implementation represents the first example of complex photonic combinatorial network for ultrafast digital processing. The network performance has been investigated for bit streams at 10 Gb/s in terms of bit error rate (BER) and contrast ratio. Moreover, the suitability of the 2times2 photonic node architecture exploiting the earlier mentioned combinatorial network has been verified at a bit rate up to 160 Gb/s. In this way, the potential of photonic digital processing for the next generation broad band and flexible interconnection networks has been demonstrated.

Abstract: A method of efficient library characterization of a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit is disclosed. The method includes determining a plurality of vectors for a plurality of arcs. Each of the plurality of vectors represents possible data bits to inputs and nodes of the logic gate. The method selects a plurality of substantially distinct vectors from the plurality of vectors for each of the plurality of arcs, and performs circuit pruning for each of the plurality of substantially distinct vectors, taking each one substantially distinct vector at a time. The circuit pruning includes identifying an active circuit for each vector. The active circuit is identified by determining which circuit features are activated when applying a particular one of the substantially distinct vectors. Then, the circuit simulations limited to a plurality of transistors in the active circuit are performed. The circuit pruning and circuit simulations are repeated for remaining ones of the plurality of substantially distinct vectors. The results of the circuit simulations are then stored on a non-volatile compute readable media, for each active circuit corresponding to each of the plurality of substantially distinct vectors.

Abstract: The power amplifier module comprises a laminate substrate comprising thermal vias and terminals, as well as a platform device with an interconnection substrate of a semiconductor material. This substrate is provided with electrical interconnects at a first side, and having been mounted on the laminate substrate with an opposite second side. Electrically conducting connections extend from the first to the second side through the substrate. A power amplifier device is attached to the second side of the substrate. One of the electrically conducting connection through the interconnection substrate is a grounding path for the power amplifier, while a thermal path is provided by the semiconductor material. There is an optimum thickness for the interconnection substrate, at which both a proper grounding and a acceptable thermal dissipation is effected.

Abstract: Systems and methods for interconnect planning which utilize probabilistic methodologies. One embodiment comprises a method for planning interconnect models in an integrated circuit design. Nets and a set of interconnect models that can be used to connect the pins of each net are first defined. For each net, the probability that each interconnect model will be used to connect the pins of the net is evaluated. Tiles in the integrated circuit design are then assigned probabilities indicating the likelihood that each of the interconnect models will traverse the tiles. A map is then generated to indicate probabilistic routing characteristics (e.g., probabilities of wire congestion, interconnect component congestion, power densities, interconnect model usage) based on the probabilities assigned to each of the tiles in the integrated circuit design. The map may then be output (e.g., printed or otherwise displayed) to a user or stored for later use.

Abstract: A mesh of trees (MoT) on-chip interconnection network has been proposed recently to provide high throughput between memory units and processors for single-chip parallel processing (Balkan et al., 2006). In this paper, we report our findings in bringing this concept to silicon. Specifically, we conduct cycle-accurate Verilog simulations to verify the analytical results claimed in (Balkan et al., 2006). We synthesize and obtain the layout of the MoT interconnection networks of various sizes. To further improve throughput, we investigate different arbitration primitives to handle load and store, the two most common memory operations. We also study the use of pipeline registers in large networks when there are long wires. Simulation based on full network layout demonstrates that significant throughput improvement can be achieved over the original proposed MoT interconnection network. The importance of this work lies in its validation of performance features of the MoT interconnection network, as they were previously shown to be competitive with traditional network solutions. The MoT network is currently used in an eXplicit multi-threading (XMT) on-chip parallel processor, which is engineered to support parallel programming. In that context, a 32-terminal MoT network could support up to 512 on-chip XMT processors. Our 8-terminal network that could serve 8 processor clusters (or 128 total processors), was also accepted recently for fabrication.

Abstract: A millimeter-wave integrated circuit (IC) package is disclosed. The package includes a substrate having a plurality of layers and a vertical interconnection. The vertical interconnection comprises a shielded transition between the plurality of layers and a compensation structure to minimize the parasitic effect of the transition.

Abstract: The semiconductor device of the present invention includes a first interconnection, a via-plug that is connected to the first interconnection, and a second interconnection that is formed as a single unit with the via-plug. The cross-sectional shape of the via-plug is such that the plug sidewall angle, which indicates the angle of the via-plug sidewall with respect to the surface of the first interconnection, is a positive angle; and moreover, at least two points exist between the base and the top of the via-plug on at least one sidewall of the two sidewalls of the cross-sectional shape of the via-plug at which the plug sidewall angle attains a maximum value. Since shapes that would give rise to the occurrence of concentrations of stress are not formed in the via-plug sidewalls, metal is more effectively embedded in the via-hole, and the incidence of voids is prevented.

Abstract: We developed a novel low-temperature chip on chip (CoC) interconnection technology featuring several thousand micro-solder bumps and a low-temperature process below 180degC. The data transfer rate between chips becomes comparable to a system on chip (SoC) by using this technology. The test chips we used had 1402 indium bumps with a diameter of 30 mum and a pitch of 60 mum. Two chips were bonded to each other while controlling the gap and growth of the intermetallic compounds (IMCs) between the two chips. We confirmed from the results of electrical evaluation that the four-terminal resistance of an indium micro bump was around 7 mOmega and the high open/short yield of micro-bump daisy-chain test element groups (TEGs). We thus successfully demonstrated low-temperature CoC technology featuring a flux-less bonding process with indium bumps. We are confident that these technologies will be indispensable to creating new applications.

Abstract: There is provided a solar cell array and a solar cell module including the solar cell array, comprising: a solar cell wafer including a semiconductor substrate and a p electrode and an n electrode provided at a surface of the semiconductor substrate; an interconnection substrate including an insulating substrate having a light receiving surface and a p interconnection and an n interconnection provided at the light receiving surface and electrically insulated from each other, on the interconnection substrate, more than one solar cell wafer being disposed adjacently, the p electrode and the p interconnection being electrically connected, the n electrode and the n interconnection being electrically connected; and an interconnection formed such that the p interconnection electrically connected to one solar cell wafer and the n interconnection electrically connected to another solar cell wafer adjacent to one solar cell wafer are electrically connected at the light receiving surface and a surface opposite thereto.

Abstract: A system and method interconnects battery packs using a flexible bus bar to prevent vibration from breaking or damaging the connections therebetween.