Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device by which a spiral inductor having a high performance and a small dominant area can be efficiently formed. SOLUTION: The method of manufacturing the semiconductor device having a plurality of interconnection layers includes a preparatory step wherein a semiconductor substrate having a plurality of semiconductor elements formed on one principal plane is prepared, a first formation step wherein spiral inductors are formed over at least three interconnection layers on the semiconductor substrate, and a second formation step wherein other circuit wiring than the spiral inductors is formed in the interconnection layers on the semiconductor substrate. The first and second formation steps are conducted at the same time. COPYRIGHT: (C)2007,JPO&INPIT

Abstract: An interconnect connection structure having first and second interconnects and multiple connection elements that electrically connect the first interconnect to the second interconnect is described. The multiple connection elements are formed laterally in a lateral region of the first and second interconnects relative to an overlay orientation of the interconnects. A central region may be free of connection elements so that electro-migration properties of the connection structure are improved and the current-carrying capacity is increased.

Abstract: In the past, traditional CMOS scaling has been one of the principal levers to achieve increased system-level performance. Today, scaling is becoming increasingly difficult and less effective, and a range of new two- and three-dimensional silicon integration technologies are needed to support next-generation systems. A silicon-carrier system-on-package (SOP) is an advanced packaging solution, enabling interconnection between ICs and other devices at densities far beyond those of current first-level packaging. Silicon-carrier employs fine pitch Cu damascene wiring, high-density solder pads/joins and high-yielding electrical through-vias. A novel approach to fabricating robust though-vias in silicon is described. The key design feature enabling large-area, uniform arrays to be produced with high yield is the annular via shape. As compared to a standard cylindrical via shape, the annular via is easier to integrate into a standard CMOS copper back-end-of-the-line (BEOL) process flow. Two process flows are compared: the first having the conductor metal within the gap of the insulated annulus itself, the second having a conducting metal core enclosed within the inner wall of the annulus. For the first process flow, two annular conductors, plated copper and CVD tungsten, are compared in terms of ease of integration, yield and susceptibility to failure during thermal stressing. Large area (45 /spl times/ 48 mm) silicon carrier modules containing more than 51,000 electrically measurable through-vias are used to compare overall yield and robustness of each process. Results on deep thermal cycling, current carrying capacity and thermomechanical modeling are discussed. Wafer-level via testing is used to statistically distinguish between via chain opens caused by bond and assembly issues versus failures in the vias or integrated wiring structures. Through-via resistances on the order of /spl sim/10 m/spl Omega/ are typical, and through-via yields of 99.98% at module level have been demonstrated.

Abstract: The semiconductor device comprises an interconnection buried in an interconnection groove formed in a lower insulating film, and an upper insulating film having a contact hole formed down to an end part of the interconnection The interconnection groove is formed by using a design pattern having a main interconnection portion 100 and an extended portion 104 provided at an end part of a main interconnection portion 100 for forming the interconnection and extended perpendicularly to an extending direction of the main interconnection portion 100

Abstract: The method of manufacturing a semiconductor device according to the present invention includes: forming an interconnect trench in an insulating film formed on a semiconductor substrate (S 100 ) ; forming a barrier metal layer on the whole surface of the insulating film (S 102 ); forming a copper layer on the whole surface of the barrier metal layer so that the copper layer is embedded in the interconnect trench (S 104 ); removing the copper layer outside the interconnect trench by polishing under a condition that the barrier metal layer is left on the surface of the insulating film (S 106 ); selectively forming a cap metal layer on the copper layer formed in the interconnect trench after the step of removing the copper layer by polishing (S 108 ); and flattening the cap metal layer by polishing (S 110 ).

Abstract: Stacked package assemblies include first and second stacked packages, each having at least one die affixed to, and electrically interconnected with, a die attach side of the package substrate. One package is inverted in relation to the other; that is, the die attach sides of the package substrates face one another, and the 'land' sides of the substrates face away from one another. Z-lnterconnectio of the packages is by wire bonds connecting the first and second package substrates. The assembly is encapsulated in such a way th both the second package substrate (one side of the assembly) and a portion of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made. In some embodiments the first package is a chip scale package, and the second package is a land grid array package.

Abstract: An interconnection structure for interconnecting circuitry on a first conductive layer to circuitry on a second conductive layer is provided. The interconnection structure of the present invention comprises a signal conductor via surrounded by a plurality of ground vias. The plurality of ground vias shield the signal conductor via, thus providing electrical isolation for the conductor via from the rest of the circuitry. One feature of the present invention is that the plurality of ground vias can be modified, adjusting their diameters and their placement relative to the signal conductor via, in order to affect the overall characteristic impedance of the interconnection structure. This feature is useful when propagating high frequency signals between signal traces on different conductive layers of a printed circuit board. In view of the high frequencies used in today's wireless communication systems, the interconnection structure proposed aids in the practical implementation of radio frequency modules by mitigating the effects of impedance discontinuities ordinarily present at signal trace-to-via transition regions.

Abstract: There is a recent surge of interest in single-chip parallel processors. In such machines, it is crucial to implement a high-throughput low-latency interconnection network to connect the on-chip components, especially the processing units and the memory units. In this paper, we propose a new mesh of trees (MoT) implementation of the interconnection network and evaluate it relative to metrics such as wire area, total switch delay and maximum throughput taking into account latencythroughput trade-offs. We show that on-chip interconnection networks can provide higher bandwidth between processors and shared first-level cache than previously considered possible, facilitating greater scalability of memory architectures that require that. MoT is also compared, both analytically and experimentally, to some other traditional network topologies, such as hypercube, butterfly, fat trees and butterfly fat trees. When we evaluate a 64-terminal MoT network at 65nm technology, concrete results show that MoT provides higher throughput and lower latency especially when the input traffic (or the on-chip parallelism) is high, at the cost of larger area. A recurring problem in networking and communication is that of achieving good sustained throughput in contrast to just high theoretical peak performance that does not materialize for typical work loads. Our quantitative results demonstrate a clear advantage of the proposed MoT network in the context of single-chip parallel processing.

Abstract: The physical layer scalability of a packet-switched optical interconnection network utilizing semiconductor optical amplifier (SOA) switch elements is investigated experimentally and with numerical modeling. Optical packets containing payloads of multiple wavelength-division-multiplexing (WDM) channels are propagated through cascaded SOA-based switching nodes in a recirculating test-bed environment. Experiments show that bit-error rates (BERs) below 10/sup -9/ can be maintained through 58 switching nodes for the entire eight-channel 10-Gb/s-per-channel payload distributed over 24.2 nm of the C-band. When the packet payload consists of a single 10-Gb/s channel, 98 node hops can be traversed before a BER of 10/sup -9/ is exceeded. In conjunction with the experiments, a novel phenomenological modeling technique is developed in order to forecast the scalability of SOA-based WDM packet interconnection networks. This technique is shown to yield results that correlate well with the experimental data. These investigations are presented as predictors of the physical limitations of large-scale WDM packet-switched networks.

Abstract: A stack package comprises a substrate having a circuit pattern; at least two semiconductor chips stacked on the substrate, having a plurality of through-via interconnection plugs and a plurality of guard rings which surround the respective through-via interconnection plugs, and connected with each other by the medium of the through-via interconnection plugs; a molding material for molding an upper surface of the substrate including the stacked semiconductor chips; and solder balls mounted to a lower surface of the substrate.

Abstract: A probe card including probes, a build-up interconnection layer having a multilayer interconnection structure therein and carrying the probes on a top surface in electrical connection with the multilayer interconnection structure, and a capacitor provided on the build-up interconnection layer in electrical connection with one of the probes via the multilayer interconnection structure, wherein the multilayer interconnection structure includes an inner via-contact in the vicinity of the probe and the capacitor is embedded in a resin insulation layer constituting the build-up layer.

Abstract: As interconnection networks proliferate to a wide range of high-performance systems, power consumption is becoming a significant architectural issue. In interconnection networks, the peak-power consumption directly affects the solution for package cooling and power-delivery design. Off-line worst-case power analysis is typically used to estimate the network peak-power consumption and guarantee safe online operation, which not only increases system cost, but also constrains network performance. In this paper, we present an online mechanism, called PowerHerd, to efficiently manage network power resources at runtime, and guarantee that network peak-power constraints are not exceeded. PowerHerd is a distributed approach-within the interconnection network, each router dynamically maintains a local power budget, controls its local power dissipation, and exchanges spare power resources with its neighboring routers to optimize network performance. Experiments demonstrate that PowerHerd can effectively regulate network power consumption, meeting peak-power constraints with negligible network-performance penalty. Armed with PowerHerd, network designers can focus on system performance and power optimization for the average case, rather than the worst-case, thus making it possible to employ a more powerful interconnection network in the system.

Abstract: The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64) is a petaflop supercomputer built on multi-core system-on-a-chip technology. Each C64 chip employs a multistage pipelined crossbar switch as its on-chip interconnection network to provide high bandwidth and low latency communication between the 160 thread processing cores, the on-chip SRAM memory banks, and other components. In this paper, we present a study of the architecture and performance of the C64 on-chip interconnection network through simulation. Our experimental results provide observations on the network behavior: (1) Dedicated channels can be created between any output port to input port of the C64 crossbar with latency as low as 7 cycles. The C64 crossbar has the potential reach the full hardware bandwidth, and exhibit a non-blocking behavior; (2) The C64 crossbar is a stable network; (3) The network logic design appears to provide a reasonable opportunity for sharing the channel bandwidth between traffic in either direction; (4) A simple circular neighbor arbitration scheme can achieve competitive performance level comparing to the complex segmented LRU (least recently used) matrix arbitration scheme without losing the fairness. (5) Application-driven benchmarks provide comparable results to synthetic workloads.

Abstract: A multilayer interconnection substrate is disclosed that includes a multilayer interconnection layer having at least a first interconnection layer and a second interconnection layer stacked with an insulating layer provided therebetween, and a connection via configured to electrically connect the first interconnection layer and the second interconnection layer. The connection via includes an internal conductor and a metal film covering the internal conductor. The internal conductor is an aggregate of metal particles.

Abstract: Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion of the polymer. The polymer layers include metal particles and the alternating metal layers and polymer layers form either a cube-shaped structure or a cylinder-shaped structure.

Abstract: A photovoltaic electrolysis (IPE) cell has a photovoltaic component and an electrolysis component which integrated, through an interconnect design, into a single unit.

Abstract: Nondestructive analysis (NDA) is one of the most important tasks that is performed during the industrial characterization of integrated circuits (ICs) because even a tiny defect or failure in the IC packages could be disastrous from the standpoint of quality control. To detect an interconnection failure in IC packages, a time-domain reflectometry (TDR) analysis system was developed. An open-end fixture (OEF) was employed to detect the rapid rise of edge signals from the package and to monitor them under the two parameters of time interval and reflection voltage. We developed a simple and effective electrical NDA system based on the TDR technology that can evaluate the interconnection of ball grid array (BGA) packages. The TDR-measurement results can determine both the failure location and type based on the aforementioned parameters for a two-die BGA package.

Abstract: As the limits of traditional CMOS scaling are approached, process integration has become increasingly difficult and resulting in a diminished rate of performance improvement over time. Consequently, the search for new two- and three- dimensional sub-system solutions has been pursued. One such solution is a silicon carrier-based System-on-Package (SOP) that enables high-density interconnection of heterogeneous die beyond current first level packaging densities. Silicon carrier packaging contains through silicon vias (TSV), fine pitch Cu wiring and high-density solder pads/joins, all of which are compatible with traditional semiconductor methods and tools. These same technology elements, especially the through silicon via process, also enable three dimensional stacking and integration. An approach to fabricating electrical through-vias in silicon is described, featuring annular-shaped vias instead of the more conventional cylindrical via. This difference enables large-area, uniform arrays to be produced with high yield as it is simpler to integrate into a conventional CMOS back-end-of-line (BEOL) process flow. Furthermore, the CTE-matched silicon core provides improved mechanical stability and the dimensions of the annular via allows for metallization by various means including copper electroplating or CVD tungsten deposition. An annular metal conductor process flow will be described. Through-via resistance measurements of 50, 90, and 150μm deep tungsten-filled annular vias will be compared. Two silicon carrier test vehicle designs, containing more than 2,200 and 9,600 electrical through-vias, respectively, were built to determine process yield and uniformity of via resistance. Through silicon via resistances range from 15-40 mΩ, and yields in excess of 99.99% have been demonstrated.

Abstract: A novel direct wafer bonding technology capable of forming a very high density of electrical interconnections across the bond interface integral to the bond process is described. Results presented include an 8 um interconnection pitch, die-to-wafer and wafer-to-wafer bonding formats, temperature cycling reliability × 10 greater than the JEDEC requirement, connection yield ∼ 99.999, > 50% part yield on parts with ∼ 450,000 connections, and < 0.1 Ohm connection resistance at 1pA without requiring a voltage surge to induce current.

Abstract: This paper presents an efficient hardware architecture for scheduling connections on a fat-tree interconnection network for parallel computing systems. Our technique utilizes global routing information to select upward routing paths so that most conflicts can be resolved. Thus, more connections can be successfully scheduled compared with a local scheduler. As a result of applying our technique to two-level, three-level and four-level fat-tree interconnection networks of various sizes in the range of 64 to 4096 nodes, we observe that the improvement of schedulability ratio averages 30% compared with greedy or random local scheduling. Our technique is also scalable and shows increased benefits for large system sizes.

Abstract: Electric power networks are usually interconnected with each other through a back-to-back direct-current (DC) link to increase reliability of electric power networks and to improve system operations. The objective of this work is to discuss the concept of a superconducting magnetic energy storage (SMES) incorporated into a back-to-back interconnection. In this case, the back-to-back system is used as a power conditioning system for the SMES coils. Since the AC/DC converter can be designed independently of the frequency of the power system, a two-way switch is connected to the AC side of each converter. This two-way switch can select the interconnected power system. By using the two-way switches, this system can increase the availability factor of the back-to-back interconnection during the SMES operations and also enables the flexible power interchange between interconnected power networks with an optimal time interval for the power demand of each interconnected power network. This work discusses the design considerations of the back-to-back interconnection with the SMES that enables the replacement of a pumped hydro storage. In this case, the SMES system is composed of a number of superconducting coils in order to decrease the risk of the superconducting coil constructions by the effect of mass production. In this work, the SMES coils are optimized from the required mass of the structure and the leakage magnetic field

Abstract: As the demands for high-density, high-speed, high-performance, and multi-function in portable electronic products, packaging technologies require significant improvement to bring out ICs' performance and shrink the total module or package size. One representative technology is to embed active devices into an organic substrate by sequential build-up processes, for example, chip-in-polymer by IZM, bumpless build-up layer by Intel, and chip-in-substrate package (CiSP) by EOL/ITRI. Through embedding the semiconductor chip in the organic substrate, the package with very good electrical performance and good capability for system integration can be realized. In this research, DDRII memory was chosen as the CiSP test vehicle, and the designed structure provides better electrical and thermal performance. Several core techniques, such as wafer thinning, die bonding, high-flatness lamination, were well developed to embed DDRII-like thin chips (50 /spl mu/m thick) into dielectric material on a carrier substrate. The PCB compatible laser drilling, via metallization, and patterning technologies were subsequently followed to form an electric path from chip-pad to outer, which provides shorter interconnection for the demand of fast electrical response application. Moreover, the vehicle was tested by lead-free reliability tests, inclusive of pre-condition (3 reflows at 260/spl deg/C), level B thermal cycle, and 168 hrs PCT tests. The newest results of the reliability tests will be presented in the paper.

Abstract: Current trends in high-performance parallel computers show that fat-tree interconnection networks are one of the most popular topologies. The particular characteristics of this topology, that provide multiple alternative paths for each source/destination pair, make it an excellent candidate for applying power consumption reduction techniques. Such techniques are being increasingly applied in computer systems and the interconnection network is not an exception, since its contribution to the system power budget is not negligible. In this paper, we present a mechanism that dynamically switches on and off network links as a function of traffic. The mechanism is designed to guarantee network connectivity, according to the underlying routing algorithm. In this way, the default routing algorithm can be used regardless of the power saving actions taken, thus simplifying router design. Our simulation results show that significant network power consumption reductions can be obtained at no cost. Latency remains the same although the number of operating network links is dynamically adjusted.

Abstract: A new flip chip interconnection structure termed BOL (bond on lead) comprising attachment of bumps to narrow pads or traces as opposed to conventional circular capture pads has been developed. The motivation for such a structure is to free up real estate for escape routing of signal lines between bumps on the topmost layer of the substrate leading to either complete elimination of layer pairs or relaxation of design rules for routing on the top layer. The reliability of the asymmetric solder joint structure so formed is investigated using hi Pb (97% lead & 3% tin) bumps and ABF (Ajinomoto build-up film, or other widely used film based high density substrates) build-up and laminate substrates by means of a test vehicle device and through finite element analysis. It is shown that the solder joints are at least as reliable as conventional solder joints; furthermore, it is found that the maximum plastic strain in the solder joint is in fact reduced by virtue of the asymmetric BOL structure which in turn increases the fatigue resistance of the solder joint as well as reduces the stress on the silicon induced by CTE (coefficient of thermal expansion) mismatch. Extended reliability studies and formal qualification results are presented. The implications of the higher routing density enabled by BOL interconnection on substrates for common device families such as GPUs, ASICs, DSPs and FPGAs are examined - it is found that an I/O (input/output) density parameter termed "effective signal escape pitch" for most devices falls in the range of 50 /spl mu/m to 110 /spl mu/m and greater than 50 % of these devices can be routed in 4 layers using BOL methodology and a microstrip transmission line architecture, while the rest can be designed so as to relax the design rules for signal escapes on the top layer of the substrate.

Abstract: A power interconnection system comprising a plurality of z-axis compliant connectors passing power and ground signals between a first circuit board to a second circuit board is disclosed. The interconnection system provides for an extremely low impedance through a broad range of frequencies and allows for large amounts of current to pass from one substrate to the next either statically or dynamically. The interconnection system may be located close to the die or may be further away depending upon the system requirements. The interconnection may also be used to take up mechanical tolerances between the two substrates while providing a low impedance interconnect.

Abstract: We propose and partially analyze a new model for determining the influence of a controller’s interconnection graph on closed-loop performance in distributed control design problems. Given a plant composed of dynamically uncoupled subsystems, we investigate the existence and properties of an optimal structured controller, when one of the weight matrices of a classical LQR cost function is topology-dependent. We also give some theoretical results as to the existence of "critical prices" at which adding supplementary edges becomes detrimental to closed-loop performance.

Abstract: Technology feasibility of MEMS-type chip I/O interconnects (namely Sea-of-Leads or SoL) is demonstrated. Acting like a spring, a MEMS lead can provide high mechanical compliance to compensate for mismatch of coefficient of thermal expansion (CTE) between a Si chip and a composite substrate. The compliant interconnects can provide low-stress connection between a chip and a PWB substrate, and, therefore, are promising to enable wafer-level packaging of IC chips with mechanically weak low-k interlayer dielectrics (ILD). The compliant interconnection also eliminates the need for an expensive underfilling process, which is one of the key challenges for scaling of conventional controlled collapse chip connection (C4) solder bumps in organic flip-chip packages. For the first time, SoL MEMS interconnects were investigated through the whole procedure of process integration, assembly, as well as reliability assessment. Without underfill, the SoL MEMS interconnects survived more than 500 thermal cycles indicating a promising improvement over a regular C4 solder joint. Failure analysis suggests that the MEMS leads do not fracture while failure occurs close to solder-Cu pad interface due to a nonreliable joining. Full reliability potential of the SoL MEMS interconnects may be demonstrated upon optimization of PWB metallurgy, soldermask design and lead compliance.

Abstract: A silicon-based system-on-package (SOP) is described. Novel capabilities of SOP are expected to enable lower cost, more efficient and higher performance electronic systems. Newly developed technology elements include: electrical silicon through-vias, fine-pitch, high bandwidth wiring, fine pitch solder interconnection, fine pitch known-good-die, and advanced microchannel cooling. Applications may range from miniaturized consumer products such as integrated function cell phones to high performance computers. SOP technology and related chip stacking challenges have been investigated and robust technology options are reported. Silicon through-vias can be fabricated using copper, tungsten, composite or alternate conductors. Via design and structure are discussed for vias in thin silicon packages mounted on a supporting substrate as well as thick silicon package that can be handled without a supporting substrate. Fine-pitch, high bandwidth wiring has been fabricated, characterized and shows greatest bandwidth for shorter interconnection distances. Fine pitch area array solder interconnections have been fabricated and characterized electrically, mechanically and with accelerated reliability testing. These fine pitch interconnections can enable the high bandwidth wiring for chip-to-chip interconnection. Integrated decoupling capacitors have been fabricated using parallel plate and trench technology. The integrated decoupling capacitors can provide under-chip, low inductance bypassing to minimize noise from simultaneous switching noise. New fine pitch, area array test technology provides a path to wafer level test for known-good-die, functional test, and burn-in for the fine pitch chip I/O. Advanced microchannel cooling can be leveraged to support high power, close proximity chips and chip stacks for cooling > 300 W/cm/sup 2/. This IBM research paper describes the design, technical challenges and progress for next generation SOP technology, chip stacking, characterization, and potential new applications.