Abstract: In a multi-layer interconnection structure, the wiring length is to be reduced, and the interconnection is to be straightened, at the same time as measures need to be taken against radiation noise. To this end, there is disclosed a semiconductor device in which plural semiconductor substrates, each carrying semiconductor elements, are bonded together. On each semiconductor substrate is deposited an insulating layer through which is formed a connection wiring passed through the insulating layer so as to be connected to the interconnection layer of the semiconductor element. On a junction surface of at least one of the semiconductor substrates is formed an electrically conductive layer of an electrically conductive material in which an opening is bored in association with the connection wiring. The semiconductor substrates are bonded together by the solid state bonding technique to interconnect the connection wirings formed on each semiconductor substrate.

Abstract: A high performance switch fabric element and flexible link interconnection topologies and frame addressing techniques therefor are disclosed. The fabric element, which may be a 16 port ASIC with internal steerable interconnection among all ports. The fabric element ports each have a unique local routing table, thereby avoiding the need for a global routing table for ports as is provided in the prior art. This also permits addressing and routing from port to port within the fabric element without need for look-up references from off the fabric element, thereby contributing to speed. The fabric element can be used in multiples interconnected by unique link interconnection techniques including cascade, mesh, microstaging, and combinations thereof. These link interconnection techniques provide unique switch topologies that permit high performance switching chassis or network box having a significantly larger number of ports than is achievable with the prior art techniques.

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

Abstract: In accordance with the objectives of the invention a new package is provided that is provided with a cavity that is shaped such that more than one semiconductor device can in a vertical direction be mounted in the cavity of the package. The devices that are mounted inside the cavity of the package are separated by separate components of insulation, the overlying devices are electrically interconnected by horizontally positioned solder bumps and vertical interconnect plugs.

Abstract: Interconnection elements for electronic components, exhibiting desirable mechanical characteristic (such as resiliency, for making pressure contacts) are formed by using a shaping tool (512) to shape an elongate core element (502) of a soft material (such as gold or soft copper wire) to have a springable shape (including cantilever beam, S-shape, U-shape), and overcoating the shaped core element with a hard material (such as nickel and its alloys), to impart to desired spring (resilient) characteristic to the resulting composite interconnection element. A final overcoat of a material having superior electrical qualities (e.g., electrical conductivity and/or solderability) may be applied to the composite interconnection element. The resulting interconnection elements may be mounted to a variety of electronic components, including directly to semiconductor dies and wafers (in which case the overcoat material anchors the composite interconnection element to a terminal (or the like) on the electronic component), may be mounted to support substrates for use as interposers and may be mounted to substrates for use as probe cards or probe card inserts. The shaping tool may be an anvil (622) and a die (624), and may nick or sever successive shaped portions of the elongate elements, and the elongate element may be of an inherently hard (springy) material. Methods of fabricating interconnection elements on sacrificial substrates are described. Methods of fabricating tip structures (258) and contact tips at the end of interconnection elements are also described.

Abstract: An architecture for a SONET network element, such as a hybrid STM/ATM add-drop multiplexer. The disclosed system includes an interconnection system for a network element, including a line unit slot, a switch fabric slot, and two or more service unit slots. The line unit slot is connected as a hub to the switch fabric slot and the service unit slots in a first star interconnection configuration. The switch fabric slot is connected as a hub to the line unit slot and the service unit slots in a second star interconnection configuration. The star interconnection configurations provide fault isolation between different units, and allow for replacement of failed units without interfering with the links of other units to the hub. In a preferred embodiment, the switch fabric slot and one of the service unit slots comprise the same slot, thus permitting flexible configuration of the device within a minimal space. In a further illustrative embodiment, a control unit slot is provided in the interconnection system, and connected as a hub to the line unit slot, the switch fabric slot, and the service unit slots to form a third star interconnection configuration. A service unit is also disclosed, including a first backplane interface for connecting with an ATM star interconnect configuration within the network element, and a second backplane interface for connecting to an STM star interconnect configuration within said network element. The service unit further includes a third backplane interface to connect with a control star interconnect configuration within the network element.

Abstract: A method of fabricating and using an interconnection element that includes a first element material adapted to be coupled to a substrate and a second element material comprising a material having a transformable property such that upon transformation, a shape of the interconnection is deformed. An example is a material that has a transformable property such that a volume of the first and/or second element material may undergo a thermal transformation from one volume to a different volume (such as a smaller volume) resulting in the deformation of the interconnection element.

Abstract: The binary hypercube, or n-cube, has been widely used as the interconnection network in parallel computers. However, the major drawback of the hypercube is the increase in the number of communication links for each node with the increase in the total number of nodes in the system. This paper introduces a new interconnection network for large-scale distributed memory multiprocessors called dual-cube. This network mitigates the problem of increasing number of links in the large-scale hypercube network while keeps most of the topological properties of the hypercube network. We investigate the topological properties of the dualcube, compare them with other hypercube-like networks, and establish the basic routing and broadcasting algorithms for dual-cubes.

Abstract: The specification describes techniques for soldering IC chips, or other components, to interconnection substrates using a patterned epoxy layer to define the solder interconnections. The epoxy layer is photodefined to form openings that expose the bonding sites on the IC chip (or alternatively the interconnect substrate). Solder paste is deposited in the openings. With the IC chip and the interconnect substrate aligned together, the solder paste is heated to reflow the solder and solder bond the IC chip to the substrate. Heating is continued to cure the epoxy, which serves the function of the conventional underfill. The shape of the solder interconnection is defined by the lithographically formed openings, and the interconnections can be made with very fine pitch. The application of the epoxy underfill in this manner assures complete filling of the gap between the IC chip and the interconnection substrate.

Abstract: Adams and Siegel (1982) proposed an extra stage cube interconnection network that tolerates one switch failure with one extra stage. We extend their results and discover a class of extra stage interconnection networks that tolerate multiple switch failures with a minimal number of extra stages. Adopting the same fault model as Adams and Siegel, the faulty switches can be bypassed by a pair of demultiplexer/multiplexer combinations. It is easy to show that, to maintain point to point and broadcast connectivities, there must be at least S extra stages to tolerate I switch failures. We present the first known construction of an extra stage interconnection network that meets this lower-bound. This 12-dimensional multistage interconnection network has n+f stages and tolerates I switch failures. An n-bit label called mask is used for each stage that indicates the bit differences between the two inputs coming into a common switch. We designed the fault-tolerant construction such that it repeatedly uses the singleton basis of the n-dimensional vector space as the stage mask vectors. This construction is further generalized and we prove that an n-dimensional multistage interconnection network is optimally fault-tolerant if and only if the mask vectors of every n consecutive stages span the n-dimensional vector space.

Abstract: A static random access memory (SRAM) device and a method for manufacturing the same are disclosed. In the SRAM device including a flip-flop circuit including two access transistors and a pair of inverters, connection lines for connecting the inputs and outputs of the inverters, and a word line, power supply lines and bit lines are formed of a metal interconnection. The resistance of interconnection can be reduced and the SRAM device manufacturing process can be performed along with CMOS standard logic manufacturing process.

Abstract: A simplified method and system for interconnecting solar cell arrays which does not utilize cause damage to the solar cells while at the same time minimizing process steps. In particular, in accordance with the present invention, interconnection between solar cell are made by way of a conductive epoxy, patterned on a substrate. The use of the epoxy eliminates the need for wire bonding as well as eliminates additional processing steps to interconnect the solar cell arrays.

Abstract: The design, packaging approach, and experimental evaluation of the free-space accelerator for switching terabit networks (FAST-Net) smart-pixel-based optical interconnection prototype are described. FAST-Net is a high-throughput data-switching concept that uses a reflective optical system to globally interconnect a multichip array of smart pixel devices. The three-dimensional optical system links each chip directly to every other with a dedicated bidirectional parallel data path. in the experiments, several prototype smart-pixel devices were packaged on a common multichip module (MCM) with interchip registration accuracies of 5-10 /spl mu/m. The smart-pixel arrays (SPAs) consist of clusters of oxide-confined vertical-cavity surface-emitting lasers and photodetectors that are solder bump-bonded to Si integrated circuits. The optoelectronic elements are arranged within each cluster on a checkerboard pattern with 125-/spl mu/m pitch. The experimental global optical interconnection module consists of a mirror and lens array that are precisely aligned to achieve the required interchip parallel connections between up to 16 SPAs. Five prototype SPAs were placed on the MCM to allow the evaluation of a variety of interchip links. Measurements verified the global link pattern across several devices on the MCM with high optical resolution and registration. No crosstalk between adjacent channels was observed after alignment. The I/O density and efficiency results suggest that a multi-terabit switch module that incorporates global optical interconnection to overcome conventional interconnection bottlenecks is feasible.

Abstract: An interconnection substrate comprises an uppermost interconnection layer having a plurality of terminal pads located at positions corresponding to a plurality of solder bumps (external connection terminals) provided on a semiconductor element which is to be mounted on the interconnection substrate. The interconnection substrate also has a metal column formed on each of the terminal pads and has a resin film covering a side surface of the metal column. The interconnection substrate further has an insulating layer formed on the uppermost interconnection layer so that a gap is formed between the insulating layer and an outer peripheral surface of the resin film.

Abstract: Precision alignment of one or more parts on a common carrier is described. A self-aligned common carrier includes a carrier substrate having one or more pockets formed in the substrate. Each pocket includes a side profile formed in the pocket. A chip having an identical side profile that complements the side profile in the pocket is mounted to the carrier substrate by inserting the chip into the pocket. The complementary side profiles result in near perfect self-alignment between the chip and at least two orthogonal planes of the carrier substrate. The chip and the carrier substrate can be made from a single crystal semiconductor material and the side profiles can be formed by anisotropic etch process that selectively etches the chip and the substrate along a predetermined crystalline plane. The chip and the carrier substrate can be single crystal silicon having a (100) crystalline orientation and the side profiles can be formed by selectively etching the silicon along a (111) crystalline plane. The matching coefficients of thermal expansion between the chip and the carrier substrate substantially reduces thermal stress related interconnect failures and misalignment between the chip and the carrier substrate. The carrier substrate and the chip can be anodically bonded to each other by oxidizing either one of the carrier substrate and the chip and etching the side profiles so that they are atomically flat.

Abstract: We design and fabricate a prototype scalable multichannel free-space interconnection module with the potential for Tb/s/spl middot/cm/sup 2/ aggregate bit-rate capacity over inter- and intra-MCM interconnection distances. The component is fabricated in a high quality optical plastic, PMMA, using deep proton lithography, an ion-based rapid prototyping technology. As a feasibility demonstration, data communication is achieved at 622 Mb/s per channel with a bit error rate smaller than 10/sup -13/ for 16 channels with an interchannel crosstalk lower than -22 dB. We perform a sensitivity analysis for misalignments and fabrication errors and study the fabrication issues of these components with injection molding techniques. Finally, we provide evidence that these modules can be mass fabricated with the required precision.

Abstract: A new bus architecture is described which is suitable for a parallel processing system without complexity of interconnection, and also drastically reduces the I/O pin count, which is highly desirable for future gigascale integrated systems. The architecture is based on the direct sequence code division multiple access (DS-CDMA) technique.

Abstract: In the present study a method of ultra-high density interconnection, the surface activation (SAB) method is introduced. Also for the next generation of packaging, which might bridge to global interconnection on chip, a concept of bump-less bonding is proposed. The bumpless bonding will be especially suitable and inevitable for ultra-high density interconnection when it will convert the range of /spl mu/m size. For such bonding requires at the same time, combinations of a ultra-thin chip and a flexible substrate. The surface activated bonding method enables the metals and non-metallic materials to be bonded at room temperature only by contact. Some fundamental experiments and preliminary results of examination of the feasibility of the method for Cu and Cu direct bonding are presented.

Abstract: To be capable of arbitrarily designing an interconnection shape of a surface layer to thereby promote reliability of connection in laminating layers and making destruction of a semiconductor element difficult to cause in a semiconductor apparatus having interconnections for connecting laminated layers on a surface and a back of a substrate and capable of laminating layers in multiple stages, a semiconductor apparatus is fabricated by a step of mounting a semiconductor element in a recess portion shallower than a thickness of a semiconductor element formed in a surface of a substrate having interconnection patterns connected by a through hole on two of the surface and a back in which a thickness of an interconnection on the surface is made thicker than a thickness of an interconnection on the back with a front thereof disposed on the lower side, a step of sealing the semiconductor element in the recess portion by synthetic resin and a step of grinding the substrate and the semiconductor element up to the interconnection on the surface.

Abstract: In interconnecting printed circuit boards: preparing a first and second printed circuit board is accomplished with the first having an insulating substrate of thermoplastic resin and a conductive pattern with a land, while the second has a conductive pattern with a land; overlapping the land of the first with the land of the second is done to form an interconnection portion; and heating the interconnection portion at a temperature approximately higher than a glass transition temperature of the thermoplastic resin while applying pressure to the interconnection portion to create an electrical interconnection sealed with a part of the thermoplastic resin constituting the insulating substrate of the first board is accomplished. The insulating substrate of the first board is overlapped with an insulating substrate of the second printed board to interpose a film, the film including material to reduce a modulus of elasticity of the insulating substrate of the first board.

Abstract: The authors propose two single-fault-tolerant gamma interconnection networks. The first is a partially chained gamma interconnection network (PCGIN) with two disjoint paths between any source-destination pair. A PCGIN has the characteristics of one fault tolerance and destination tag routing, but backtracking may be necessary when a fault occurs. To eliminate the backtracking penalties of a PCGIN, a fully chained gamma interconnection network (FCGIN); that can at least tolerate one link or switch fault at each stage without backtracking, is also proposed FCGIN has the advantages of destination tag routing, lower hardware costs than a PCGIN, low fault penalty, and strong reroutability.

Abstract: A interconnection structure of the damascene type is produced on a surface of a microelectronic device that includes at least one dielectric material layer for housing at least one interconnection and at least one interface layer on the dielectric material layer. The interface layer may include at least one SiCH layer and at least one SiOCH layer.

Abstract: The detectability of interconnection opens by logic and I/sub DDQ/ testing is investigated. Opens in interconnection paths disconnect the driven gate(s) from the driving gate. An electrical model for interconnection opens is used to predict the detectability of this type of open. Using the proposed model, explicit analytical expressions have been obtained to determine the conditions for reliable detection of this defect by logic and I/sub DDQ/ testing. The cases of full controllability and non-full controllability of the signals at the coupling lines have been analysed. The effect of the trapped charge during fabrication has also been investigated. In addition, it has been found that the detectability of interconnection opens depends on the metal level where the signals are laid-out. The detectability dependency of interconnection opens on the test generation process has been analyzed.

Abstract: A method is provided for forming a conductive interconnect, the method comprising forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer, and forming a first conductive structure in the first opening. The method also comprises forming a second dielectric layer above the first dielectric layer and above the first conductive structure, forming a second opening in the second dielectric layer above at least a portion of the first conductive structure, the second opening having a side surface and a bottom surface, and forming at least one barrier metal layer in the second opening on the side surface and on the bottom surface. In addition, the method comprises removing a portion of the at least one barrier metal layer from the bottom surface, and forming a second conductive structure in the second opening, the second conductive structure contacting the at least the portion of the first conductive structure. The method further comprises forming the conductive interconnect by annealing the second conductive structure and the first conductive structure.

Abstract: The present invention relates generally to an electrical interconnection package and a method thereof. More particularly, the invention encompasses an invention that increases the fatigue life of a Ball Grid Array (BGA) electrical interconnection. This invention structurally couples at least one module to an organic interposer using a high modulus underfill material. The organic interposer is then joined to a organic board using standard joining processes. The inventive module can then be removed from the organic board at any time by moving the organic interposer using standard rework techniques.

Abstract: A proposal is presented for an effective extraction method for crosstalk model parameters of high-speed interconnection lines. In the extraction procedure, mutual capacitance and mutual inductance of the coupled interconnection lines are extracted based on S-parameter measurement, time-domain-reflectometry (TDR) measurement and subsequent microwave network analysis. The extraction method is useful for characterizing homogeneous guiding structures, where the propagation of coupled transverse electromagnetic (TEM) modes is supported. In contrast to previous extraction methods, the suggested procedure requires fewer on-wafer probing steps and does not need matched terminations in the test device for high-frequency probing. The extracted models can be readily used with simulation program with integrated circuit emphasis (SPICE) circuit simulation. The procedure can also be used for modeling the crosstalk in packaging structures and multichip modules (MCMs). The proposed procedure has been successfully applied to the crosstalk model extraction of on-chip interconnection lines. Crosstalk model parameters were obtained for different line structures, spaces, and widths. Finally, the validity and reliability of the extracted models were examined by comparing a SPICE circuit simulation using the extracted crosstalk model parameters with high-speed time-domain crosstalk measurement. A close agreement was observed in the amplitude and pulse shape between the simulation and the measurement, showing the accuracy and usefulness of the proposed extraction method.

Abstract: In a semiconductor integrated circuit device, upon connection of an interconnection made of aluminum or aluminum alloy and another interconnection made of Cu or Cu alloy, a barrier conductor film or plug is disposed at the joint portion between these interconnections. Among the interconnection layers, the uppermost one is made of a wiring material such as aluminum or aluminum alloy, while the lower one is made of Cu or Cu alloy. The lowest interconnection is made of a conductive material other than Cu or Cu alloy. For example, the conductive material which permits minute processing and has both low resistance and high EM resistance such as tungsten is employed.

Abstract: Current joining technology especially used for electronic products, such as soldering, wire bonding, thermo-compression bonding, adhesive bonding, are not used to be designed for dismantling, even though rework or repair is indispensable in practical applications. In this paper, the concept of active disassembly and reversible interconnection is critically reviewed by considering the bonding and debonding mechanism of the materials interfaces. Disassembly process is characterized both by disassembly energy and disassembly entropy. Active disassembly is defined as such disassembly operations using an active mechanism which is built-in to the assembly macroscopically or microscopically, or even in the material itself to reduce the necessary energy and/or entropy for disassembly. The reversible interconnection is a concept for interconnection method which enables the products to be assembled and disassembled reversibly. Active assembly can be used for realizing a reversible interconnection. Several new attempts to develop a method for reversible interconnection are presented. The bonded interface is weakened by segregation of alloying elements, or by hydridation of hydrogen storage alloy used as bonding intermediate which becomes very brittle or pulverized by absorbing hydrogen. Also, selectivity of disassembly can be achieved by using temperature dependence of the phenomena of hydrogen absorption. Examples are shown to demonstrate how the concept is applied to electronic products or dismantling PWB assemblies.