Abstract: The advantages of the invention are realized by a chip-on-chip module having at least two fully functional chips, electrically connected together, and a chip-on-chip component connection/interconnection for electrically connecting the fully functional chips to external circuitry.

Abstract: An integrated circuit type device having a series of bond pads for the interconnection of the device with external power or communication lines, a method of improving the registration accuracy of the interconnection comprising the step of forming a guide rail on the device spaced adjacent to the bond pads for abutting the external power and communication lines against so as to accurately position the lines for interconnection with the bond pads. Preferably, the bond pads are arranged in a line along one edge of the integrated circuit type device and the lines are in the form of a Tape Automated Bonding strip. The guide rail can be formed utilising a standard micromechanical systems deposition process and is ideally utilized in a pagewidth ink jet printing system.

Abstract: This disclosure provides a multiple chip assembly where multiple chips are stacked on top of one another using relatively low melting temperature solder balls. Preferably, the chips (either packages or flip chip attachment) are each mounted to a substrate which is larger in lateral surface area than the associated chip. Each substrate thus has a free area, not masked by the chip, which is utilized to mount a vertically-adjacent substrate. Within this free area, solder balls connect the substrates to provide for vertical logic bus propagation through the assembly and vertical heat dissipation. The solder balls are made to have a relatively low melting temperature, permitting interconnection between chip/substrate layers without affecting connection between chip and substrate or with an intervening carrier. At the same time, the layers are compressed together during such interconnection to bring a thermal transport layer in contact between the bottom of each substrate and the chip of an underlying layer, to facilitate lateral heat dissipation.

Abstract: Recent deregulation of telecommunications in the US and elsewhere has highlighted the importance of interconnection in network industries In this paper, we analyze interconnection in a deregulated network where the participants compete in the final retail market We consider both the case of a mature industry as well as one where a new entrant challenges the incumbent In the latter case, network externalities allow the incumbent to use the terms of interconnection to maintain its dominant position Moreover, in either case, competition in the retail market can be undermined by collusion over access prices We discuss the implications for some of the provisions of the new US Telecommunications Act, specifically mandatory interconnection and reciprocity of tariffs, comparing these to the simple "bill and keep" rule

Abstract: Interconnection elements for electronic components, exhibiting desirable mechanical characteristics (such as resiliency, for making pressure contacts) are formed by shaping an elongate element (core) of a soft material (such as gold) to have a springable shape (including cantilever beam, S-shape, U-shape), and overcoating the shaped elongate element with a hard material (such as nickel and its alloys), to impart a desired spring (resilient) characteristic to the resulting composite interconnection element. A final overcoat of a material having superior electrical qualities (e.g., electrical conductivity and/or solderability) may be applied to the composite interconnection element. The elongate element may be formed from a wire, or from a sheet (e.g., metal foil). The resulting interconnection elements may be mounted to a variety of electronic components, including directly to semiconductor dies and wafers (in which case the overcoat material anchors the composite interconnection element to a terminal (or the like) on the electronic component), may be mounted to support substrates for use as interposers and may be mounted to substrates for use as probe cards or probe card inserts. In one embodiment, a hybrid composite interconnection element is formed by mounting a core to an end of an flat elongate element formed from a sheet, and overcoating at least the core, the flat elongate element providing a "floating" support for the overcoated core, capable of absorbing non-planarities (tolerances) of an electronic component. Methods of fabricating interconnection elements on sacrificial substrates are described. Methods of fabricating tip structures and contact tips at the end of interconnection elements are described.

Abstract: The specification describes techniques for attaching double sided circuit boards having plated through holes to interconnection substrates using solder bump arrays. The through holes are filled with a high melting point solder which allows solder bumps to be located directly on the through hole thus saving board area and reducing the interconnection length.

Abstract: An integrated circuit includes at least one porous silicon oxycarbide (SiOC) insulator (140, 305), which provides low dielectric constant (e.g., eR < 2) for minimizing parasitic capacitance. The insulator provides IC isolation, such as between circuit elements (115), between interconnection lines (300, 315), between circuit elements (115) and interconnection lines (300, 315), or as a passivation layer (320) overlying both circuit elements and interconnection lines.

Abstract: This paper reviews a number of low-swing on-chip interconnect schemes, and presents a thorough analysis of their effectiveness and limitations. In addition, several new interface circuits, presenting even more energy savings, are proposed. Some of these circuits not only reduce the interconnect swing, but also use very-low supply voltages, so as to obtain quadratic energy savings. The performance of each of the presented circuits is thoroughly examined using simulation on a benchmark interconnect circuit. Energy savings with a factor of seven have been observed for some of the schemes.

Abstract: We model and compare on-chip (up to wafer scale) and off-chip (multichip module) high-speed electrical interconnections with free-space optical interconnections in terms of speed performance and energy requirements for digital transmission in large-scale systems. For all technologies the interconnections are first modeled and optimized for minimum delay as functions of the interconnection length for both one-to-one and fan-out connections. Then energy requirements are derived as functions of the interconnection length. Free-space optical interconnections that use multiple-quantum-well modulators or vertical-cavity surface-emitting lasers as transmitters are shown to offer a speed–energy product advantage as high as 30 over that of the electrical interconnection technologies.

Abstract: A universal multi-chip interconnect system using a set of at least two types of standardized interconnect components is disclosed. One of the component types comprises a chip carrier capable of holding at least one IC chip in a first portion thereof and providing a plurality of standardized interconnections from the first portion to one or more second portions of the carrier, where one or more interconnect components of a different type may be connected. Another of the component types comprises a bridge connector which is capable of connecting to two or more chip carriers at their second portions. Each bridge connector has at least two interconnect portions which are capable of connecting to chip carriers at their second portions, and a standardized pattern of interconnect wires between the interconnect portions. Once a set of chip carriers and bridge carriers are assembled in a desired arrangement, a plurality of potentially-active interconnect paths are formed, the total number of which exceeds the number interconnection paths needed by the system. The particular selection of the interconnect paths needed to implement the system's interconnection is accomplished by routing the I/O signals of each IC chip to the pads of the carrier which are coupled to interconnect paths which will provide the desired system interconnectivity. The routing may be accomplished by customizing the interconnect-metalization layer of the and/or by forming a customized pattern of solder bumps (or equivalent connectors) between the IC chip and the surplus-pad chip carrier, and/or other methods disclosed herein.

Abstract: A programmable logic device has logic array blocks (“LABs”) and interconnection resources. For interconnecting signals to, from, and between the LABs, the global interconnection resources may include switch boxes, long lines, double lines, single lines, and half- and partially populated multiplexer regions. The LAB includes two levels of function blocks. In a preferred embodiment, there is one four-input second-level function block for every four-input first-level function blocks. At least one tri-state buffer is provided in each LAB. Each tri-state buffer may receive a data signal either from one or more function blocks in the associated LAB or from one or more interconnection conductors adjacent to the LAB. The tri-state buffer may buffer one of the received data signals and apply the resulting buffered signal to one or more of the interconnection conductors adjacent to the LAB.

Abstract: Interconnect traffic between local exchange carrier (LECS) networks and other carrier networks, particularly competitive local exchange carrier (CLEC) networks, dictates a need for efficient monitoring and analysis of the interconnect traffic. In accord with the invention, monitor equipment on the LEC network captures call related messages produced by the LEC network and compiles data from those messages to form call detail records for the interconnect traffic. These records are loaded into a relational database. A data preparation routine enhances the data, for example, by translating certain codes from the records into more useful text and by spreading or binning usage over predefined time intervals. An on-line analytical processing program runs one or more applications to allow the LEC to analyze the interconnect traffic between the LEC network and the other carrier's network. The analysis provides useful traffic data for accounting purposes, e.g. for use in determining jurisdictional factors for reciprocal compensation calculations. The data also enables the LEC to engineer upgrades of the network to provide cost effective service for the traffic to and from the other carrier's network.

Abstract: An electronic device that is equipped with a plurality of bonding pads positioned on the device for making electrical interconnections and electrically conductive composite bumps adhered to the bonding pads wherein the bumps are formed of a composite material consisting of a thermoplastic polymer and at least about 30 volume percent of conductive metal particles based on the total volume of the metal particles and the thermoplastic polymer. The present invention is also directed to a method of making electrical interconnections to an electronic device by pressing a plurality of composite bumps of a polymeric based material against a substrate having an electrically conductive surface by mechanical means under a sufficient temperature and/or a sufficient pressure. The present invention is further directed to a method of debonding an electronic device bonded by a composite binder by first providing an electronic device that is bonded by composite bumps consists of a thermoplastic polymer and at least about 30 volume percent of conductive metal particles and then exposing the composite bumps to a solvent or to a temperature not less than about 50%° C. below the glass transition temperature of the composite bump.

Abstract: An interconnect and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The interconnect includes a substrate with patterns of contact members adapted to electrically contact the contact bumps. The substrate can be formed of a material such as ceramic, silicon, FR-4, or photo-chemically machineable glass. The contact members can be formed as recesses covered with conductive layers in electrical communication with conductors and terminal contacts on the substrate. Alternately, the contact members can be formed as projections adapted to penetrate the contact bumps, as microbumps with a rough textured surface, or as a deposited layer formed with recesses. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.

Abstract: The specification describes a recessed chip IC package in which the cavity in the printed wiring board into which the IC chip is recessed is used as a through hole interconnection, thus increasing the interconnection density. If the through cavity interconnections are used as power and ground the signal I/O pads and the signal runners are effectively isolated.

Abstract: The development of 2-D array transducers has received much recent interest. Unfortunately, fabrication of high density 2-D arrays is difficult due to the large number of electrical interconnections which must be made to the back side of the elements. A typical array operating at 2.2 MHz may have 256 or more connections within a 16.4 mm circular footprint. Interconnection becomes even more challenging as operating frequencies increase. To solve this problem, we have developed a multilayer flexible (MLF) circuit interconnect consisting of a polyimide dielectric with inter-laminar vias routing signals vertically and etched metal traces routing signals horizontally. A transducer is fabricated from an MLF by bonding a PZT chip to its surface and dicing the chip into individual elements, with the saw kerf extending partially into the top polyimide layer to ensure physical and electrical isolation of the elements. The KLM model was used to compare the performance of an MLF 2-D array to a conventional hand wired 2-D array. MLF and wire guide transducers were fabricated, each with 256 active elements, 0.4 mm interelement spacing, and 2.2 MHz center frequency. Vector impedance, pulse length, bandwidth, angular response, and cross-coupling were found to be comparable in both types of arrays. Using the MLF, however, fabrication time was reduced dramatically. More importantly, MLF technology may be used to increase 2-D array connection density beyond the limitations of current of hand wired fabrication techniques. Thus MLF circuits provide a means for the interconnection of current and future high frequency 2-D arrays.

Abstract: The specification describes interconnection layouts for chip-on-chip packages using solder bump interchip connections as vias between a single level metal interconnection pattern on the lower support IC chip and another single level interconnection pattern on the upper IC chip This arrangement allows for the formation of air isolated crossovers of features on either chip

Abstract: A method which utilizes flip chip technology to provide interconnection between printed circuit boards and integrated circuits is disclosed The method involves metallization of the bond pad and multiple, novel bump compositions and coating compositions to provide an interconnection which is reliable and which withstands differences in the coefficient of thermal expansion between the silicon device and the bump material

Abstract: Programmable interconnection group arrangements for selectively interconnecting logic on a programmable logic device are provided. Interconnection groups may be programmed to route signals between the various conductors on the device, and to route signals from various logic regions on the device to the various conductors. The interconnection groups provide routing flexibility and efficiency without using excessive amounts of interconnection resources.

Abstract: Coplanar waveguides were fabricated in a process that emulates silicon CMOS technologies with 5 to 10 metal layers. The observed S/sub 21/ loss of 0.3 dB/mm at 50 GHz is among the lowest ever reported with standard Al interconnects on Si/SiO/sub 2/. Optimum design parameters were counter-intuitive: in some frequency ranges, the lowest loss was achieved with relatively narrow lines over a low-resistivity substrate. This was exploited in the design of transmission lines that are fully compatible with a CMOS technology. The process emulation was calibrated with a commercial 4-layer Al/Cu CMOS technology.

Abstract: A semiconductor device has an air-gap/multi-level interconnection structure. The interconnects are insulated from one another by an air gap in the same layer, and by an interlevel dielectric film between layers and from a semiconductor substrate. A high-speed semiconductor device is obtained due to a lower parasitic capacitance.

Abstract: This paper describes the design and performance of an 80-Gbit/s 2:1 selector-type multiplexer IC fabricated with InAlAs/InGaAs/InP HEMTs. By using a double-layer interconnection process with a low-dielectric insulator, microstrip lines were designed to make impedance-matched, high-speed intercell connection of critical signal paths. The record operating data rate was measured on a 3-in wafer. In spite of the bandwidth limitation on the measurement setup, clear eye patterns were successfully observed for the first time. The obtained circuit speed improvement from the previous result of 64 Gbit/s owes much to this high-speed interconnection design.

Abstract: Chip-on-chip interconnections of varied characteristics, such as varied diameters, heights and/or composition, are disclosed A first chip-on-chip interconnection on a joining plane has a first characteristic (eg, a first height) and a second chip-on-chip interconnection on the same joining plane has a second characteristic (eg, a second height greater than the first height) The first and second characteristics of the chip-on-chip interconnections allow for chip-on-chip connections to other packages, substrates or chips of different levels and/or compositions

Abstract: Projected performance metrics of free-space optical and electrical interconnections are estimated and compared in terms of smart-pixel input-output bandwidth density and practical geometric packaging constraints. The results suggest that three-dimensional optical interconnects based on smart pixels provide the highest volume, latency, and power-consumption benefits for applications in which globally interconnected networks are required to implement links across many integrated-circuit chips. It is further shown that interconnection approaches based on macro-optical elements achieve better scaling than those based on micro-optical elements. The scaling limits of micro-optical-based architectures stem from the need for repeaters to overcome diffraction losses in multichip architectures with high bisection bandwidth. The overall results provide guidance in determining whether and how strongly a free-space optical interconnection approach can be applied to a given multiprocessor problem.

Abstract: An interconnection device used with test probe equipment for connecting a vertical-pin integrated circuit probing device to external test equipment The interconnection device comprises a probe card with a pattern of contacts, a mounting plate adjustably mounted to the probe card and a space transformer member attached to both the mounting plate and the probe card The space transformer carries traces which connect a small pattern of pins on the probing device with a larger pattern of conductors on the probe card The space transformer is a laminated impedance-matching member comprising two layers of beryllium copper separated by a thin dielectric adhesive

Abstract: The present invention relates to multilevel integrated circuit interconnection techniques. An integrated circuit having a number of electronic components along a semiconductor substrate and a first connection layer having a first number of conductors in selective electrical contact with the components is provided. A first insulative layer is formed on the first connection layer with a first pattern of openings therethrough. A second connection layer is established that has a second number of conductors selectively interconnected to the first conductors through the first pattern of openings. A second insulative layer is formed on the first connection layer with a second pattern of openings therethrough. A third connection layer is formed on the second insulative layer having a third dielectric and a third number of conductors selectively interconnecting the second conductors. The first and second insulative layers are preferably etch selective to a dielectric included in the first, second, and third connection layers; and crossover, crossunder, or local interconnects are formed in a different connection layer than routing interconnects to facilitate higher interconnection density.

Abstract: A module interconnection system which minimizes electronic signal propagation delays is disclosed. The module interconnection system includes a backplane (20), a first plurality of connectors (30) arranged in a side by side generally parallel arrangement (32, 34, 36, 38), and a second plurality of connectors (40) arranged in a side by side generally parallel arrangement (41, 42, 43, 44, 45, 46, 47, 48, 49, 50). In a preferred embodiment, the second plurality of connectors (40) are mounted on the backplane (20) at right angles to the first plurality of connectors (30) so as to provide short routing paths between each of the second plurality of connectors (40) and at least one of the first plurality of connectors. Point-to-point signal interconnections are selectively utilized to provide data paths between selected contacts of at least one of the first plurality of connectors (30) and selected contacts of the second plurality of connectors (40). The above described interconnection apparatus permits high speed data communication between modules disposed in at least one of said first plurality of connectors and at least one module disposed in said second plurality of connectors.

Abstract: An arrangement for coupling a first packaged integrated circuit to a second packaged integrated circuit comprises a first packaged integrated circuit that includes a first set of electrical interconnection elements arranged on a first surface and a second set of electrical interconnection elements arranged on a second surface which is opposite to the first side. A thermally conductive material is disposed on the second surface and the second set of electrical interconnection elements are arranged around at least a portion of the periphery of the second surface. A second packaged integrated circuit includes a third set of electrical interconnection elements arranged on a first surface of the second packaged integrated circuit. The third set of electrical interconnection elements are shaped to mechanically and electrically couple and decouple to or from the second set of electrical interconnection elements non-destructively by application of manual force.