Abstract: The performance of most digital systems today is limited by their communication or interconnection, not by their logic or memory. As designers strive to make more efficient use of scarce interconnection bandwidth, interconnection networks are emerging as a nearly universal solution to the system-level communication problems for modern digital systems. Interconnection networks have become pervasive in their traditional application as processor-memory and processor-processor interconnect. Point-to-point interconnection networks have replaced buses in an ever widening range of applications that include on-chip interconnect, switches and routers, and I/O systems. In this book, the authors present in a structured way the basic underlying concepts of most interconnection networks and provide representative solutions that have been implemented in the industry or proposed in the research literature. * Gives a coherent, comprehensive treatment of the entire field * Presents a formal statement of the basic concepts, alternative design choices, and design trade-offs * Provides thorough classifications, clear descriptions, accurate definitions, and unified views to structure the knowledge on interconnection networks * Focuses on issues critical to designers Table of Contents Foreword Foreword to the First Printing Preface Chapter 1 - Introduction Chapter 2 - Message Switching Layer Chapter 3 - Deadlock, Livelock, and Starvation Chapter 4 - Routing Algorithms Chapter 5 - CollectiveCommunicationSupport Chapter 6 - Fault-Tolerant Routing Chapter 7 - Network Architectures Chapter 8 - Messaging Layer Software Chapter 9 - Performance Evaluation Appendix A - Formal Definitions for Deadlock Avoidance Appendix B - Acronyms References Index

Abstract: High density packaging of semiconductor devices on an interconnection substrate is achieved by stacking bare semiconductor devices atop one another so that an edge portion of a semiconductor device extends beyond the semiconductor device that it is stacked atop. Elongate interconnection elements extend from the bottommost one of the semiconductor devices, and from the exposed edge portions of the semiconductor devices stacked atop the bottommost semiconductor device. Free-ends of the elongate interconnection elements make electrical contact with terminals of an interconnection substrate, such as a PCB. The elongate interconnection elements extending from each of the semiconductor devices are sized so as to reach the terminals of the PCB, which may be plated through holes. The elongate interconnection elements are suitably resilient contact structures, and may be composite interconnection elements comprising a relatively soft core (e.g., a gold wire) and a relatively hard overcoat (e.g., a nickel plating).

Abstract: In a first inter-layer insulator film above source/drain regions of basic cells constituting a gate array, first contact holes (joint contacts) are placed, so that wings (joint plates) electrically connected with the source/drain regions via plugs in those joint contacts is locally placed above the source/drain regions. Above the wings is formed a second inter-layer insulator film, above which is formed a first level interconnection which constitutes one of metal wiring layers. In the second inter-layer insulator film are formed second contact holes, so that a semi-custom ASIC is provided in which the wings and the first level interconnection are electrically interconnected via the plugs in those second contact holes. The first and second contact holes, first level interconnection, etc. are automatically designed by use of a computer based on a grid pattern in the basic cells. According to the present invention, the basic cells need not be re-designed even if a first pitch of a pattern of the first contact holes is different from a second pitch of a pattern of the second contact holes, thus easily enabling automatic customization. Without increasing the area of the source/drain regions in the basic cells, any pitch of the wiring layers can be selected, thus increasing the integration density without deteriorating the performance of MOS FETs at the same time as reducing time required for the customization.

Abstract: A ball grid array to integrated circuit interconnection. The interconnection includes a ball grid array substrate having a first surface and a second surface. The first surface comprising a plurality of substrate interconnection conductive pads. A power supply via connects a power supply conductive pad of the first surface to a first conductive area on the second surface. A ground via connects a ground conductive pad of the first surface to a second conductive area on the second surface. A decoupling capacitor connected between the first conductive area and the second conductive area. The interconnection further comprises an integrated circuit comprising a plurality of integrated circuit conductive pads. A plurality of smaller solder balls interconnect at least one of the integrated circuit conductive pads to at least one of the substrate interconnection conductive pads. A circuit board substrate is electrically interconnected by larger solder balls to the ball grid array substrate.

Abstract: Fault-tolerant systems aim at providing continuous operation in the presence of faults. Multicomputers rely on an interconnection network between processors to support the message-passing mechanism. Therefore, the reliability of the interconnection network is very important for the reliability of the whole system. This paper analyzes the effective redundancy available in a wormhole network by combining connectivity and deadlock freedom. Redundancy is defined at the channel level. We propose a sufficient condition for channel redundancy, also computing the set of redundant channels. The redundancy level of the network is also defined, proposing a theorem that supplies its value. This theory is developed on top of our necessary and sufficient condition for deadlock-free adaptive routing. The new theory also considers the failure of physical channels when virtual channels are used. Finally, we propose a methodology for the design of fault-tolerant routing algorithms, showing its application to n-dimensional meshes.

Abstract: The paper considers the power constrained design of orthogonal multiprocessor interconnection networks. The authors present a detailed model of message latency as a function of topology, technology architecture, and power. This model is then used to analyze a number of interesting scenarios, providing a sound engineering basis for interconnection network design in these cases. For example, they have observed that under a fixed power constraint, the network dimension which achieves minimal latency is a slowly growing function of system size. In addition, as they increase the available power per node for a fixed system size, the dimension at which message latency is minimized shifts towards higher dimensional networks.

Abstract: An integrated free-space optical interconnection system with 2500 parallel data channels is demonstrated. The design is based on a combination of microchannel imaging and conventional imaging. A modification of the hybrid imaging configuration allows one to achieve optimized image quality over large image fields.

Abstract: Contact tip structures are fabricated on sacrificial substrates for subsequent joining to interconnection elements including composite interconnection elements, monolithic interconnection elements, tungsten needles of probe cards, contact bumps of membrane probes, and the like. The spatial relationship between the tip structures can lithographically be defined to very close tolerances. The metallurgy of the tip structures is independent of that of the interconnection element to which they are attached, by brazing, plating or the like. The contact tip structures are readily provided with topological (small, precise, projecting, non-planar) contact features, such as in the form of truncated pyramids, to optimize electrical pressure connections subsequently being made to terminals of electronic components. Elongate contact tip structures, adapted in use to function as spring contact elements without the necessity of being joined to resilient contact elements are described. Generally, the invention is directed to making (pre-fabricating) relatively ‘perfect’ contact tip structures (“tips”) and joining them to relatively ‘imperfect’ interconnection elements to improve the overall capabilities of resulting “tipped” interconnection elements.

Abstract: A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.

Abstract: An active-matrix liquid crystal display integrally formed with a driver circuit including: a pair of substrates disposed in opposing relation to each other; and a liquid crystal material sandwiched between the pair of substrates, wherein the pair of substrates includes: a TFT substrate including at least an insulative substrate, source interconnection line and gate interconnection line which are formed in a matrix pattern on the insulative substrate, a thin film transistor provided to each pixel portion for use as a switching element for applying a voltage to a portion of the liquid crystal material which lies at a location where the source interconnection line and the gate interconnection line intersect each other, a pixel electrode connected to a drain electrode of the thin film transistor for supplying a voltage to the liquid crystal material, and a CMOS driver circuit having a CMOS which comprises thin film transistors for supplying an electric signal to the thin film transistor of the pixel portion through the source interconnection line and the gate interconnection line; and a counterpart substrate including an insulative substrate and a counter electrode formed thereon, the thin film transistor provided to the pixel portion being of a first conductivity type and of an offset or LDD structure, at least a first conductivity type thin film transistor of the thin film transistors of the CMOS driver circuit being of an offset or LDD structure.

Abstract: A network server includes removable network interface modules mounted in a chassis. The network interface modules connect to a CPU through an interconnection assembly module. The network interface modules may comprise removable canisters containing a plurality of interface cards.

Abstract: A comprehensive system and method allow an integrated circuit designer to extract accurate estimates of parasitic impedances in interconnection lines of an integrated circuit. The method includes collecting values of electrical characteristic parameters to provide a technology profile for a particular fabrication process. An Interconnect Primitive Library builder provides a collection of interconnect `primitives` that any interconnect structure fabricated under the fabrication process can be broken down into, and combines it with the technology profile for simulations in a 3-dimensional field solver to extract parameterized coupling capacitances and other characteristic impedances for each interconnect primitive. An extraction tool traces a signal path of an integrated circuit and decomposes the interconnect structures on the signal path into interconnect primitives and maps them to the Interconnect Primitive Library. An RC network module provides an RC network based on the characterized parametric values in the mapped interconnect primitives. The RC network thus provided can be used to accurately estimate signal delays in a circuit simulator or delay calculator.

Abstract: Modular power supply apparatus wherein a plurality of d.c.-to-d.c. converters are coupled to an internally structured heat exchange channel through which fan driven air is passed in an unobstructed manner along a flow axis. Each of the converter modules is combined with a dedicated module circuit board which provides regulated output terminals in an orientation or direction arranged transversely to the flow axis. The opposite end of the module circuit boards are plugged into a main interconnect circuit board positioned along one side of the heat exchange channel. A support channel is provided outwardly of the main interconnect circuit board within which principal components of supporting circuitry are contained.

Abstract: The claimed data protection device (20) includes a processor (22) connected to a memory system (24) through an interconnection mechanism (26). An input device (28) is also connected to the processor (22) and memory system (24) through the interconnection mechanism (26). The interconnection mechanism (26) is typically a combination of one or more buses and one or more switches. The output device (30) may be a display, and the input device (28) may be a keyboard and/or mouse or other cursor control device.

Abstract: A method for forming an interconnection pattern in a semiconductor device for reducing metallic reflection, includes the steps of forming a conductive layer on a substrate, polishing the conductive layer to form a rugged surface on the conductive layer, and selectively removing the polished conductive layer to form the interconnection pattern.

Abstract: Interconnection elements for electronic components, exhibiting desirable mechanical characteristics (such as resiliency, for making pressure contacts) are formed by using a shaping tool (512) to shape an elongate core element (502) of a soft material (such as gold or soft copper wire) to have a springable shape (including cantilever beam, S-shape, U-shape), and overcoating the shaped core element with a hard material (such as nickel and its alloys), to impart a desired spring (resilient) characteristic to the resulting composite interconnection element. A final overcoat of a material having superior electrical qualities (e.g., electrical conductivity and/or solderability) may be applied to the composite interconnection element. The resulting interconnection elements may be mounted to a variety of electronic components, including directly to semiconductor dies and wafers (in which case the overcoat material anchors the composite interconnection element to a terminal (or the like) on the electronic component), may be mounted to support substrates for use as interposers and may be mounted to substrates for use as probe cards or probe card inserts. The shaping tool may be an anvil (622) and a die (624), and may nick or sever successive shaped portions of the elongate element, and the elongate element may be of an inherently hard (springy) material. Methods of fabricating interconnection elements on sacrificial substrates are described. Methods of fabricating tip structures (258) and contact tips at the end of interconnection elements are also described.

Abstract: A flip-chip interconnection technology which enables reduction of strain in the bumps and uniform encapsulation of underfill resin has been developed by applying the advanced copper column based solder bumps ' The solder bump has a copper column at the center of its bottom and is designed for high reliability flip-chip interconnection The copper column shape and the solder volume were obtained by employing FEM (Finite Element Model) simulation to analyze the plastic strain in the solder bumps In the fabrication process, a microstructural resist patterning technique to form the copper column precisely was developed Also, the electroplating technique to control the copper column shape and solder volume has been developed by utilizing voltammetric analysis The relations between the encapsulant flow and encapsulation bump layout design parameters were obtained by the evaluation of encapsulation flow characteristics under the LSI chip based on the laminar model Concerning reliability, the thermal fatigue lifetime of the flip-chip interconnection was found to be equal to or longer than that of the conventional interconnection

Abstract: Network interconnection is provided by the appropriate combination and use of repeaters, bridges, routers and gateways. Each of these relays has different capabilities and so it is important to choose the one best suited to the task.Repeaters interconnect similar LAN segment to form a single extended LAN, bridges interconnect similar LANs to form a single subnetwork, routers interconnect subnetworks to form a single network, gateways interconnect different networks to form an integrated network.

Abstract: A method and apparatus for characterizing dimensions and parasitic capacitance between integrated-circuit interconnects are disclosed. The apparatus is a test structure including at least two substantially identical oscillators, at least two substantially identical counters, and a pulse generator. Each of the oscillators is connected to an integrated-circuit interconnect. Each of the counters is coupled to a respective oscillator. The pulse generator is utilized to inject a series of fixed-length clock pulses to each of the oscillators such that the parasitic capacitance of the integrated-circuit interconnects can be characterized by the ratio of oscillation periods of the oscillators to parasitic capacitances of the integrated-circuits.

Abstract: In this paper a technique is described for the measurement of the correct S-parameters of an N-port package or interconnection using a 2-port network analyzer with 50 /spl Omega/ system impedance and N imperfect terminations. The technique is fully general and can be applied using arbitrary terminations. Broadband 50 n loads are not required. The method is illustrated on a coupled microstrip line structure.

Abstract: A data parallel processing system is equipped with two or more processing elements. On termination of data processing, each processing element informs an interconnection device of it. The interconnection device produces serial data on the basis of information indicating a progress of data processing by each of processing elements connected to it and information about the placement and configuration of the processing elements, then broadcasts the serial data to each of the processing elements. At this point, serial data of the shortest length is produced in such a way that processing elements not connected to the interconnection device or not in a ready state are omitted.

Abstract: A fluidic micro actuator array with through-the-wafer interconnection is fabricated. Actuators are composed of micro cantilevers over through holes. Cantilevers pass/cut the air flow which is applied from the backside via the through hole nozzles. Each through hole is also used for electrical interconnection by evaporating Au metal on it. The actuator array is assembled with an IC controller to construct an autonomous distributed conveyance system.

Abstract: PROBLEM TO BE SOLVED: To reduce the size of a semiconductor device by making a structure in which external terminals are formed in a semiconductor chip area SOLUTION: A semiconductor device comprises a circuit board including a circuit pattern between an outer insulating layer with external terminals and an inner insulating chip-mount layer having an inner interconnection area 13; a semiconductor chip 2 having electrodes on its front surface and bonded to the inner insulating layer on its back; wires 3 for making connections between the electrodes of the semiconductor chip 2 and the inner interconnection area 13; and a resin molding 4 that seals the semiconductor chip 2 and the wires 3 on the circuit board The inner interconnection area 13 is formed around the semiconductor chip 2, and the interconnection pattern 7 is located between the chip and the interconnection pattern

Abstract: An improved interconnection ball joint for a ball grid array integrated circuit package includes a substrate base having a first surface to which an integrated circuit die is affixed, and an opposite second surface. A metallized via extends through the substrate. The via has a central hole which extends through the substrate. The hole is plugged with a flexible nonconductive material, such as epoxy solder mask material. A metallic interconnection ball land is on the second surface of the substrate, integral with the metallized via and adjacent to the hole and the plug of nonconductive material. A solder interconnection ball is formed on the land, opposite the via and the plug of nonconductive material. A metal-to-metal annular bond is formed at the joint between the interconnection ball and the land around the plug of nonconductive material in the center of the via. The joint has an unexpectedly high shearing strength, and resists cracking, which reduces risks of a electrical connectivity failure at the joint. Location of the interconnection ball directly opposite the via allows miniaturization of the package.

Abstract: A routing switch for constructing an interconnection network of a parallel processing computer is disclosed. A purpose of the present invention is to provide a crossbar routing switch for a hierarchical interconnection network which has an expandability of a data length and an expandability of a hierarchical structure. The crossbar routing switch for a hierarchical interconnection network in accordance with the present invention comprises a predetermined number of input control units for controlling one input port to perform the manipulation of input data; a crossbar core unit for analyzing a data transmission request by the input control unit and outputting the corresponding data; and a predetermined number of output control unit for controlling one output port and receiving the output data from the crossbar core unit to output it to the output port. The present invention has advantages over the prior art that a data expandability can be provided by simply adding a routing switch without re-designing or re-manufacturing the routing switch several times, and that it can be suitably adapted to an interconnection network of a parallel processing system which requires a high expandability and high performance.