Abstract: A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process An embodiment comprises the simultaneous formation of a via and trench in a single etching step

Abstract: A process for electrolessly depositing cobalt-tin alloys with adjustable tin contents from 1 to over 25 atomic percent tin is disclosed. The deposited alloy is useful in the electronics and computer industries for device, chip interconnection and packaging applications. When used for chip interconnection applications, for example, the invention replaces the currently used complicated ball-limiting-metallurgy. The invention may also be used to inhibit hillock formation and electromigration in copper wire structures found in computers and micron dimension electronic devices.

Abstract: The chemical mechanical polishing (CMP) of selective aluminum (Al) CVD via plugs is examined for the first time and a fully planarized four-level interconnection system with all stacked via plugs is demonstrated. A sandwich of Ti/TiN/Ti barrier layers with an Al-CVD plug has proved to be one of the best via plug structures because of its low via resistance and extremely high reliability. Quarter-micron 120-kG gate array LSIs have been successfully fabricated using a 1.4 /spl mu/m, equal pitch, four-level interconnection.

Abstract: We examine electrical performance issues associated with advanced VLSI semiconductor on-chip interconnections or “interconnects.” Performance can be affected by wiring geometry, materials, and processing details, as well as by processor-level needs. Simulations and measurements are used to study details of interconnect and insulator electrical properties, pulse propagation, and CPU cycle-time estimation, with particular attention to potential advantages of advanced materials and processes for wiring of high-performance CMOS microprocessors. Detailed performance improvements are presented for migration to copper wiring, low-e dielectrics, and scaled-up interconnects on the final levels for long-line signal propagation.

Abstract: Advances in interconnection technology have played a key role in allowing continued improvements in integrated circuit density, performance, and cost. ibm contributions to interconnection technology over approximately the last ten generations of semiconductor products are reviewed. the development of a planar, back-end-of-line (beol) technology, used in ibm dram, bipolar, and cmos logic products since 1988, has led to a threefold increase in the number of wiring levels, aggressive wiring pitches at all interconnection levels, and high-leverage design options such as stacked contacts and vias. possible future beol technologies are also discussed, with emphasis on the use of higher-conductivity wiring and lower-dielectric-constant insulators. it is expected that their use will result in higher performance and reliability. applications include future, lower-power devices as well as more cost-effective, higher-performance versions of present-day designs.

Abstract: The present invention relates generally to a new apparatus and method for use in chip, module, card, etc., burn-in and/or test or electrical interconnection. More particularly, the invention encompasses an apparatus that is used as a temporary media between a chip, module, card, etc., that needs to be tested and/or burned-in and a test or burn-in system. A method for such burn-in and/or test or electrical interconnection is also disclosed. The invention also encompasses an apparatus and a method that can be used as a permanent media between two electrical devices, such as, for example, between a chip and a module or a card, etc., that is to be contained in and part of a system.

Abstract: High conductivity interconnection lines are formed of high conductivity material, such as copper, employing barrier layers impervious to the diffusion of copper atoms. Higher operating speeds are obtained with conductive interconnection lines, preferably copper interconnection lines, formed above the wire bonding layer.

Abstract: An apparatus and method for determining how to interconnect a plurality of components of a system, given a limited number of interconnect resources available to a device. First, it is determined whether the system meets the capacity constraints of the device. If the requirements exceed the capacity, a larger device is necessary. Otherwise, a topmost interconnection level is established. This topmost level is partitioned into four different partitions. The components are assigned and optimized to these four partitions. Next, a lower level of interconnection is established for one or more of these four partitions. Each of these lower levels are, in turn, partitioned into four different partitions. Components are then assigned and optimized to these partitions. This process is repeated for even lower levels until routing of the interconnections for the system is achieved. Thereupon, the components are physically interconnected from the lower levels to the topmost level according to the routing pattern that was determined in the establishing, partitioning, and said optimizing steps.

Abstract: The present invention provides an overhead balanced electricity distribution and/or power transmission network (1201), the network including input means (1301) for the input onto the network of a telecommunications signal having a carrier frequency greater than approximately 1MHz from an unbalanced source and output means (1301) for removing said telecommunications signal from the network, wherein said input means and said output means provide impedance matching between said network and said source. Thus, propagation of HF communication signals over such networks is optimised, and the input and output means ('conditioning units') provide for interconnection between a source e.g. a relatively low impedance unbalanced HF (possibly coaxial) termination and a high impedance balanced OH EDN, and provide efficient unbalanced to balanced impedance transformation and termination.

Abstract: A semiconductor device including a plurality of chip units each defined by a side wall and arranged in a state such that a side wall of a chip unit abuts a corresponding side wall of an adjacent chip unit, and an interconnection structure for interconnecting a plurality of terminals of a side wall of a chip unit to corresponding terminals of a side wall of an adjacent chip unit that abuts the chip unit at the respective side walls.

Abstract: Signal communication paths between multiple chips are established through inter-chip electro-magnetic coupling, thereby potentially eliminating mechanical inter-chip contacts and increasing inter-chip interconnection capacity while maximizing chip real estate allocated to a circuit layer. In one embodiment, multiple chips each include a conductive layer, disposed over a circuit layer on a substrate, divided into electro-magnetic coupling device elements such as capacitor plates. When utilizing capacitor plates, chips are arranged face-to-face with opposing chips having mirror image capacitor plate patterns to form a plurality of capacitors. Conventional signal transmission circuits produce time-varying signals which propagate to conventional signal receiving circuits of another chip via an embodiment of electro-magnetic signal communication paths formed by the capacitors. In another embodiment, one of the chips may function as a passive chip carrier that includes a conventional communication path between sets of capacitor plates that capacitively interconnect multiple chips that are facially opposed to the chip carrier. In another embodiment, chips having a capacitive interconnect layer can be combined into arrays with each array arranged in an offset, face-to-face spatial orientation with respect to at least one other array. Because the arrays are offset, one chip may be capacitively coupled to more than one other chip. As a result, any chip may communicate with any other chip by propagating a transmitted signal from chip to chip via capacitor links until received by a destination chip.

Abstract: Demands for increased interconnection density and higher bandwidth, coupled with stringent cost constraints of advanced wide bandwidth telecommunication switching equipment, are exhausting conventional electrical interconnection capabilities The requirement for greater interconnection capabilities, spawned in part by the advances in integrated circuit technologies and the need for enhanced digital services, dictate that technology advancement must occur in traditional electronic packaging and/or interconnection techniques The resolution of these technological needs is paramount for the successful competitive introduction of these systems Presently, a "bottle-neck" occurs at the board-to-board level of the interconnection hierarchy Therefore, an opportunity exists for the development of new optical interconnection techniques which can be incorporated into system designs beginning at this interconnection level and beyond The strategic insertion of optical interconnection technology into these electronic processing systems not only meets projected performance requirements, but potentially offers them at a competitive cost This paper describes some of the new optical strategies switching equipment designers are incorporating into today's products These strategies range from optical data links to an implementation of a flexible optical backplane called OptiFlex >

Abstract: A structural shape has an injection molded, three-dimensional substrate composed of an electrically insulating polymer, polymer studs planarly arranged on the underside of the substrate and co-formed during injection molding, outside terminals formed on the polymer studs by a solderable end surface, interconnections fashioned at least on the underside of the substrate that connect the outside terminals to inside terminals, and at least one chip arranged on the substrate and whose terminals are electrically conductively connected to the inside terminals. The structural shape is suitable for single, few or multi chip module and unites the advantages of a ball grid array with the advantages of MID technology (Molded Interconnection Devices). The manufacture and metallization of the polymer studs can take place with minimal additional outlay in the framework of the method steps already required in the MID technology.

Abstract: There is shown an apparatus for switching. The apparatus for switching comprises L switching modules which switch packets, where L≧2 and is an integer. In an embodiment, each of the L switching modules switch packets independent of any other switching module such that there is distributed switching of packets across the L switching modules. The apparatus also comprises an interconnection module which is connected to each of the L switching modules. The interconnection module that provides a passive backplane provides connectivity between the L switching modules. In an embodiment, the interconnection module provides space and time multiplexed connectivity between the L switching modules. In an other embodiment, the interconnection module is expandable without a priori knowledge of a final number of switching modules. In yet another embodiment, the interconnection module is reprogrammable in regard to connectivity between the L switching modules. The present invention pertains to a method for creating a switching apparatus. The method comprises the steps of connecting a first and at least a second switching module to an interconnection module. Next, there is the step of programming the interconnection module to create a desired connectivity between the first and second switching modules to the interconnection module. Then, there is the step of transferring a packet through the interconnection module and first and second switching modules. Then, there is the step of connecting at least one additional switching module to the interconnection module. Next, there is the step of reprogramming the interconnection module to create a desired connectivity between the first, second and third switching modules to the interconnection module. The present invention pertains to a method of directing a packet.

Abstract: Electronic power conversion circuitry, for frequencies not exceeding 30 MHz, is manufactured using the benefits of low temperature co-fired ceramic substrates to provide interconnection between the discrete components of the power conversion circuit, and integrate various non-semiconductor devices into the body of the low temperature co-fired ceramic structure, such as resistors, capacitors, inductors and transformers. Use of a low temperature co-fired ceramic structure as a substrate on and within which power conversion circuitry is formed allows selection of various conductive and resistive inks to precisely form interconnection circuitry and selected non-semiconductor components which improves the stability and reduces the cost of power conversion circuits.

Abstract: Recent high-density very large scale integrated (VLSI) interconnections in multichip modules require high-reliability solder interconnection to enable us to achieve small interconnect size andlarge number of input/output terminals, and to minimize soft errors in VLSIs induced by α-particle emission from solder. Lead-free solders such as indium (In)-alloy solders are a possible alternative to conventional lead-tin (Pb-Sn) solders. To realize reliable interconnections using In-alloy solders, fatigue behavior, finite element method (FEM) simulations, and dissolution and reaction between solder and metallization were studied with flip-chip interconnection models. We measured the fatigue life of solder joints and the mechanical properties of solders, and compared the results with a computer simulation based on the FEM. Indium-alloy solders have better mechanical properties for solder joints, and their flip-chip interconnection models showed a longer fatigue life than that of Pb-Sn solder in thermal shock tests between liquid nitrogen and room temperatures. The fatigue characteristics obtained by experiment agree with that given by FEM analysis. Dissolution tests show that Pt film is resistant to dissolution into In solder, indicating that Pt is an adequate barrier layer material for In solder. This test also shows that Au dissolution into the In-Sn solder raises its melting point; however, Ag addition to In-Sn solder prevents melting point rise. Experimental results show that In-alloy solders are suitable for fabricating reliable interconnections.

Abstract: An automated external defibrillator which automatically performs self-tests on a daily and weekly basis. Tested functions include the presence and interconnection of defibrillator electrodes, battery charge state and the operability of the high voltage circuit. Visual and audible indicators are actuated to alert an operator if faults are identified. A record of each self-test is stored in memory, and can be subsequently retrieved through a communications port.

Abstract: We address the two-pole simulation of interconnect trees via the moment matching technique. We simulate the interconnect network by modeling the distributed lines with non-uniform m lumped segments and using the two-pole methodology. To this end, we derive new non-uniform equivalent circuits which match the general distributed line transfer function up to the second term. Using the recursive equation for the admittance of a tree, we give the exact expressions for the first and second moments of the transfer function of the interconnect tree. Our results show that delay estimates using our method are within 13% of SPICE-computed delays. As routing trees become bigger and interconnection lines become longer, e.g., in MCM design, our approach has advantages in both accuracy and simulation complexity.

Abstract: Parallel simulation is emerging as the dominant technique for studying parallel computers. However the interconnection networks of these machines can be modeled at many different levels of abstraction, allowing researchers to trade off accuracy and performance. We use the Wisconsin Wind Tunnel, a parallel simulator for cache-coherent shared-memory machines, to study the trade-offs of accuracy versus performance for six different network simulation models. We evaluate these models for a variety of parallel applications, cache-coherence protocols, and topologies. We show that only the two most expensive models-which model contention at individual links-are robust in the presence of high network loads or non-uniform traffic patterns. >

Abstract: In a semiconductor device and a method of fabrication thereof, a resin film forms an interlayer film of the semiconductor device having a multilayer interconnection structure, and is formed by only one coating using coating liquid containing silicone ladder polymers represented by the chemical formula: (HO) 2 (R 2 Si 2 O 3 ) n H 2 . As a result, it is possible to improve long-term reliability of electric characteristics or the like, and simplify a process.

Abstract: PURPOSE:To prevent the remaining material of an interconnection layer from forming a short circuit by a method wherein the interconnection layer on a substratum insulating layer is patterned, an interconnection in a desired pattern is formed and the material of the interconnection layer remaining outside an interconnection region is oxidized and transformed into an electric insulator CONSTITUTION:An interconnection layer is formed of polysilicon on a field SiO2 oxide film 18 and a gate SiO2 oxide film 19 as substratum insulating layers, and interconnections 22, 24 in desired patterns are formed by an RIE method In this case, the etching condition of the RIE method is adapted to the thickness T' of the interconnection layer That is to say, the RIE method is executed under the etching condition where the cross section of an interconnection after an etching operation does not shape an overhang Consequently, even after the RIE method has been executed, the polysilicon remains in a stringer shape outside the region of the interconnection region In succession, the remaining polysilicon is oxidized and transform into SiO2, so that an electric insulator D is formed Thereby, it is possible to prevent an electric short circuit from being formed between interconnections

Abstract: A method for estimating current or detecting defects in an interconnection by monitoring current change of the interconnection. A radiation beam such as a laser, electron or ion beam is irradiated to a subject region to be observed while scanning points of the subject region. Decrease of the supply current during the scanning is detected in the power supply line. The amount of decrease is approximately proportional to the current flowing originally. The value of the current in the interconnection or a defect existing in the interconnection can be estimated or found from the decreased amount. One of or the combination of selective scanning, threshold selection and thin film deposition makes it possible to apply this method to an actual device.

Abstract: A film carrier semiconductor device 10 comprises a semiconductor bare chip 20 and a carrier film 30. Chip electrodes 21 are provided on the bare chip 20. Each chip electrode 21 is electrically connected to the carrier film 30. Bump electrodes 37 are formed and arranged as an array on the carrier film 30 on the side of the other surface 31b of the film 30. Interconnection layers 32 are provided on the carrier film 30 to connect some of the chip electrodes 21b to the bump electrodes 37a and 37b. The semiconductor device 10 also comprises a noise blocking layer 60 provided on the carrier film 30 outside the chip mounting region. The noise blocking layer 60 is electrically connected to at least one of the chip electrodes 21a.

Abstract: A prototype multiprocessor system using three-dimensional board-to-board free-space optical interconnects is constructed for the first time to our knowledge. In the system, 64 processing units form a three-dimensional mesh processor network with the help of bidirectional board-to-board free-space optical interconnects. A theoretical analysis shows that the three-dimensional board-to-board free-space optical interconnects effectively solve common interconnection problems such as wiring congestion, signal delay, and clock skew. The prototype system, COSINE-III, is confirmed to work well as a multiprocessor system. The system is also shown to be easy to extend to a larger and more flexible system.

Abstract: A chip carrier for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer, having plated photo-vias, to electrically interconnect two (or more) layers of fan-out circuitry. This chip carrier further employs a single-tiered cavity to contain a chip, rather than a multi-tiered cavity, as is conventional. Moreover, this chip carrier includes thermal via holes and/or a metallic layer, directly beneath the chip, to enhance heat dissipation.

Abstract: A packet switching architecture provides for a switch system comprised of a cellular base station in communication with the PSTN through a switch. Data packets are routed through the switch system as necessary to effect communication between the public switched telephone network (PSTN) and mobile radiotelephones disposed within the cellular coverage area surrounding the base station. A packet interconnection subsystem operates to transfer data packets between a plurality of interface ports, to which are coupled a corresponding plurality of signal lines. Within the interconnection subsystem, one or more distribution/consolidation (DISCO) interface units are mutually coupled together through a central router unit. Each DISCO interface unit is configured to consolidate the data packets received through at least two signal ports onto a consolidation bus, as well as to distribute the addressed data packets from a distribution bus to two or more of ports. In a preferred implementation, the interconnection subsystem is realized so as to efficiently provide redundancy among the interface units within the interconnection network.

Abstract: A novel, high performance, high reliability interconnection structure for an integrated circuit. The interconnection structure of the present invention is formed on a first insulating layer which in turn is formed on a silicon substrate or well. A first multilayer interconnection comprising a first aluminum layer, a first refractory metal layer, and a second aluminum layer is formed on the first insulating layer. A second insulating layer is formed over the first multilayer interconnection. A conductive via is formed through the second insulating layer and recessed into the first multilayer interconnection wherein a portion of the via extends above the second insulating layer. A second interconnection is formed on the second insulating layer and on and around the portion of the via extending above the second insulating layer.