Abstract: The present invention is directed to a structure (2) for packaging electronic devices, such as semiconductor chips (36, 38), in a three dimensional structure which permits electrical signals to propagate both horizontally and vertically. The structure is formed from a plurality of assemblies (4, 6). Each assembly is formed from a substrate (8) having disposed on at least one surface a plurality of electronic devices. Each assembly is disposed in a stack of adjacent assemblies. Between adjacent assemblies there is an electrical interconnection means (49) electrically interconnecting each assembly. The electrical interconnection means is formed from an elastomeric interposer. The elastomeric interposer is formed from an elastomeric material having a plurality of electrical conductors extending therethrough, either in a clustered or un-clustered arrangement. The electrical interconnection means is fabricated having a plurality of apertures extending therethrough. The array of apertures corresponds to the array of electronic devices on the substrates. The aperture and electrical interconnection means is disposed over the array of electronic devices so that the electrical interconnection means is between adjacent electronic devices. The stack of assemblies is compressed thereby compressing the electrical interconnection means between adjacent assemblies. The substrate of each assembly is formed from a thermally conductive material such as diamond. A heat dissipation means is thermally connected to the edges of the substrate to extract heat generated within the structure. Methods for fabricating the electrical interconnection means as a stand alone elastomeric sheet are described. The ends (50, 54) of the plurality of conductors in the electrical interconnection means (49) are fabricated so that upon compression between adjacent assemblies (4, 6) there is a wiping action between the conductor ends (e.g. 50) and contact locations (e.g. 30) on the adjacent assemblies to form a good electrical contact therewith.

Abstract: A local area network including cabling interconnecting a plurality of workstations, the cabling including a plurality of data ports and conductors for selectable and removable interconnection between selected ones of the data ports and apparatus for automatically providing an indication of the connection pattern of the data ports.

Abstract: The work describes, from a switching system designers perspective, present digital interconnection technologies and needs. The discussion begins at the chip-to-chip interconnection level and proceeds to the frame-to-frame level. The authors evaluate the optimal packaging and interconnection technology that should be used in future system designs. The analysis suggests that parallel optical data links based on a laser array technology implemented at the board-to-board level are presently advantageous. This analysis, as well as a detailed description of laser gate arrays, is also included. >

Abstract: Free-space interconnection of widely spaced pixels may be implemented using microlenses, rather than conventional imaging. Advantages, problems, and studies of system capacity are discussed.

Abstract: Cellular neural networks or CNNs are a novel neural network architecture introduced by Chua and Yang which is very general and flexible, has some important properties desirable for design applications and can be efficiently implemented on custom hardware based on analogue VLSI technology. In this paper an abstract normalized definition of cellular neural networks with arbitrary interconnection topology is given. Instead of stability, the property of convergence is found to be of central importance: large classes of convergent CNNs in practice always asymptotically approach some stable equilibrium where each component of the corresponding output is binary-valued. A highly efficient CMOS-compatible CNN circuit architecture is then presented where a basic cell consists of only two fully differential op amps, two capacitors and several MOSFETs, while a variable interconnection weight is realized with only four MOSFETs. Since all these elements are standard components in the current analogue IC technology and since all network functions are implemented directly on the device level, this architecture promises high cell and interconnection densities and extremely high operating speeds.

Abstract: A semiconductor device having a multilayer interconnection structure includes a tungsten plug buried in a contact hole formed in an interlayer insulating film covering first aluminum interconnection with a first titanium film and a first titanium nitride film interposed therebetween, and second aluminum interconnection formed thereon with a second titanium film and a second titanium nitride film interposed therebetween. According to this structure, remaining particles of an alterated layer of aluminum formed on the surface of the first aluminum interconnection are removed, and the first aluminum interconnection reacts with the first titanium film to form an intermetallic compound, so that mixing of the interface between them is carried out. Coverage of the contact hole is improved by burying the tungsten plug.

Abstract: A method for providing vias, lines and other recesses in VLSI interconnection structures with copper alloys to create a thin layer of an oxide of an alloying element on the surface of the deposited alloy and on portions of the alloy which are in contact with an oxygen containing dielectric is disclosed. The present invention is also directed to VLSI interconnection structures which utilize this copper alloy and thin oxide layer in their vias, lines and other recesses. The oxide layer eliminates the need for diffusion barrier and/or adhesion layers and provides corrosion resistance for the deposited copper alloy. VLSI devices utilizing this copper alloy in the vias, lines and other recesses interconnecting semiconductor regions, devices and conductive layers on the VLSI device are significantly improved.

Abstract: The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.

Abstract: A prototype digital free-space photonic switching fabric is demonstrated. It consists of three cascaded 16 x 8 arrays of symmetric self-electro-optic-effect devices that are used as logic gates that implement part of a multistage interconnection network. We discuss architecture, device tolerancing, optical system design, and optomechanical design. This optical circuit is successfully configured as a fully operational array of 32 independent 2 x 2 nodes and operates at 100 kHz.

Abstract: An interconnection system and method of testing and performing burn-in of semiconductor devices prior to separation from the semiconductor wafer on which the devices are formed includes forming interconnection layers of contacts and conductors over the devices and then testing and performing burn-in on the devices. Faulty devices are disconnected from the conductors prior to performing additional test and burn-in. The interconnections are removed prior to separating the device on the wafer, and prior to further possible tests and packaging.

Abstract: PURPOSE:To reduce a drop in a power-supply voltage due to the capacity, the contact resistance and the like of an interconnection and to supply the stable voltage to an integrated circuit as a whole even when the area of the integrated circuit is made large by a method wherein a power-supply interconnection is arranged at the outer circumferential part of the integrated circuit. CONSTITUTION:A power-supply interconnection 101 is arranged between the outer circumference of an integrated circuit and a pad. When a plurality of pads 102 having the same potential exist inside the integrated circuit, the respective pads are made in common by using the power-supply interconnection arranged at the circumferential part. A power supply is fed to an internal circuit from an interconnection 103 arranged between the pads; it can be supplied also from a power-supply pad 104 by using an interconnection material. In order to stabilize a power-supply voltage, a passivation film in one part of the interconnection arranged at a corner part of the integrated circuit is removed in the same size as a bonding pad, and it is used as a pad 105 exclusively for power-supply feeding use. Thereby, it is possible to avoid the lack of uniformity, of a voltage, which is easily caused in the corner part inside the integrated circuit, and it is possible to stabilize the power-supply voltage.

Abstract: A noniterative time-dependent circuit model is presented for transient analysis of general uniform and nonuniform interconnection structures terminated with arbitrary, linear or nonlinear loads. Simulated or measured scattering parameter data are used to characterize the interconnection structures. No approximations or model fitting are required. At each point in time, all coupled ports of the interconnection structure are modeled as extended Thevenin equivalents, which consist of constant resistances and time-dependent voltage sources. This new general circuit representation is compatible with existing simulation programs such as SPICE. Simulations on circuits with linear and nonlinear loads illustrate the approach. >

Abstract: A noniterative time-dependent circuit model is presented for transient analysis of general uniform and nonuniform interconnection structures terminated with arbitrary, linear or nonlinear loads. Simulated or measured scattering parameter data are used to characterize the interconnection structures. No approximations or model fitting are required. At each point in time, all coupled ports of the interconnection structure are modeled as extended Thevenin equivalents, which consist of constant resistances and time-dependent voltage sources. This new general circuit representation is compatible with existing simulation programs such as SPICE. Simulations on circuits with linear and nonlinear loads illustrate the approach. >

Abstract: A computer-aided analysis system has been established to calculate the equivalent inductance and resistance matrices for three-dimensional multiconductor interconnection structures. Based on partial element equivalent circuit theory, the interconnection structures are first decomposed into many straight segments which are of circular or rectangular cross sections but can be in arbitrary orientation. The resistances and partial inductances between all these segments are calculated using analytical integration and quadrature formulae. They are assembled into the desired equivalent impedance matrix by general network theory. Illustrative examples include the analysis for nonuniformly coupled transmission lines and the calculation for skin-effect impedances of transmission lines and three-dimensional structures. The numerical results are in good agreement with the measurement data and results in the literature. >

Abstract: Solder interconnection for forming connections between an integrated semiconductor device and a carrier substrate is provided Located on the carrier substrate are electrodes and located between the electrodes and integrated semiconductor device are solder connections that have a relatively low melting point such that when the device is in operation, the solder connection will liquify thereby permitting expansion compensation between the substrate and semiconductor device

Abstract: A three-dimensional integration technology that electrically connects an independently optimized thin-film device layer to a Si circuitry layer is reported. An epitaxial liftoff GaAs thin-film optical detector is integrated directly on top of Si amplifier circuitry with a planarizing, insulating layer of polymide between the detector and the circuitry. The detector is virtually connected to the circuitry below through an electrical via in the insulator. This integration technology enables monolithic, massively parallel vertical interconnection between two independently optimized device layers. Systems such as image processing arrays should significantly benefit from this massively parallel integration technology. >

Abstract: An adaptation device (90) and method allows an efficient interconnection of data processing devices (91,92) and networks (93,94). It is based on layer 2 connectivity of entities complying with various High-level Data Link Control (HDLC) protocols, including LAPD and LAPB protocols.

Abstract: Techniques for driving long interconnections in VLSI circuits are considered. Methods based on regularly inserted repeaters are reviewed, and it is shown that one of these is optimal. The main conclusions are that with the most accurate model of an interconnection (a pi -model) used, the optimal repeater is an appropriately sized inverter and that, when the interconnection is resistive, a double-stage repeater performs better than an exponential horn of inverters. >

Abstract: This paper describes a bump-fabrication process for a fine pitch and high aspect ratio bump array. The fabricated bumps had a 10 pm pitch with a 5 Dm diameter and a 20 D m height, and were arranged 5 pm apart from each other. The bumps were made of a copper base pillar and a solder cap, and were located on the device circuit area to realize high reliability flip-chip interconnections. A microstructual resist patterning technique to form a fine pitch and high aspect ratio bump array has been developed. The characteristics of the positive type photoresist were investigated to explicate the fundamental behaviors by evaluating the alkaline solubility and the dissolution effect. Also, the factors which affect the resist patterning accuracy were also elucidated to obtain precise resist pattern.

Abstract: A digital crossbar switch designed to facilitate easy and flexible interconnection of up to 8 data ports. The device includes 8 bidirectional ports, each 8 bit wide. Interconnection of the ports is controlled by 32 stored control memory locations associated with each port. The controlling memory locations can be changed dynamically without interfering with data flow. Additional program flexibility can be achieved by providing each port with a 16 word first-in first-out data buffer. The capability to bit reverse the data on any of the ports is also provided to simplify the interconnection of busses from different architectures. The device is fully expandable to wider busses, has extensive test capability and a master reset is provided for system initialization.

Abstract: An improved wafer-wide optical bus interconnect is described for use in wafer-scale integration systems. By optically coupling sub-systems on the wafer, faults normally found in electrically based interconnection topologies are avoided. The invention incorporates a planar waveguide which couples emitters and detectors distributed throughout the wafer. The waveguide transmits an omnidirectional emission from an optical diode to all detectors on the wafer. The only electrical connection between sub-systems on the wafer may be for power.

Abstract: A semiconductor integrated circuit device has an interconnection structure in which multilayer aluminum interconnection layers are connected through connection holes. A first aluminum interconnection layer is formed on a main surface of the semiconductor substrate. The first aluminum interconnection layer has a surface layer which includes any of high melting point metal, high melting point metal compound, high melting point metal silicide, or amorphous silicon. An insulating layer is formed on the first aluminum interconnection layer, and has a through hole if formed extending to a surface of the first aluminum interconnection layer. A second aluminum interconnection layer is formed on the insulating layer and is electrically connected to the surface layer of the first aluminum interconnection layer through the through hole. The second aluminum interconnection layer includes a titanium layer, a titanium nitride layer and an aluminum alloy layer. The titanium layer is formed on the insulating layer to be in contact with the surface of the first aluminum interconnection layer through the through hole. The titanium nitride layer is formed on the titanium layer. The aluminum alloy layer is formed on the titanium nitride layer. An electrical contact resistance between the first and second aluminum interconnection layers is stabilized, and resistance against the electron-migration and stress-migration is improved in the interconnection structure.

Abstract: The selective electroless Ni-Cu(P) deposition process has been investigated for via hole filling and conductor pattern cladding in VLSI multilevel interconnection structures Cu was added to Al-Si in order to deposit Ni-Cu(P) on Al-Si-Cu lines without any activation step and obtain a good selectivity It was observed that a 02 μm Ni-Cu(P) overcoat on a 05 μm Al-Si-Cu line increases corrosion resistance, suppresses hillock formation, and decreases the resistance of interconnection

Abstract: The authors present an analysis of a novel low-cost, post-attach bypassing technique called close attached capacitor (CAC), which offers an attractive alternative to managing switching noise in single or multichip packages. The CAC is a thin flat capacitor, comparable in size to an IC die, that is placed on the active surface of the die and connected to onchip power and ground pads through very short bonds. By locating the CAC on the face of the die, the inductance of chip bonds and associated outer lead bond pads is avoided and less interconnect area is needed. Some environmental testing of the CAC process has been performed, indicating no device parameter degradation when attachment is made to the active surface of a passivated die. CAC design issues are addressed, and the feasibility of manufacturing high-frequency capacitors and their assemblies using conventional reworkable or permanent attach processes is demonstrated. Examples of the integration of CACs in high-performance single chip packages and to chips on multichip modules are shown, and the effectiveness of CACs in the reduction of switching noise is demonstrated. >

Abstract: A modular transconductance-mode (T-mode) design approach is presented for analog hardware implementations of neural networks. This design approach is used to build a modular bidirectional associative memory network. The authors show that the size of the whole system can be increased by interconnecting more modular chips. It is also shown that by changing the interconnection strategy different neural network systems can be implemented, such as a Hopfield network, a winner-take-all network, a simplified ART 1 network, or a constrained optimization network. Experimentally measured results from CMOS 2- mu m double-metal, double-polysilicon prototypes (MOSIS) are presented. >

Abstract: The performance evaluation of multistage self-routing interconnection networks for asynchronous transfer mode (ATM) switching is carried out by means of an analytical approach. The switching elements in the interconnection network are provided with a buffer shared among all the inlets and outlets of the element and no backpressure signals are exchanged between adjacent stages. Two analytical models are considered: the scalar model and the vectorial model. In the former case the addresses of the packets in the same buffer are assumed to be mutually independent, whereas in the latter case the model keeps memory of the addresses of the packets stored in the buffer across consecutive time slots. The vectorial model provides performance measures much more accurate than the scalar model. >

Abstract: Feasibility study results on direct chip interconnection (DCI) using anisotropic conductive polymer material on both flexible and rigid substrates are discussed. The concept is to simultaneously attach and electrically interconnect IC chips to circuit traces. When conductors are joined under heat and pressure to form a bond, metallic spheres within the adhesive layer make contact with both surfaces but not each other, causing the anisotropic conductivity. Since process parameters (such as temperature, pressure, and cure time) as well as chip/substrate registration are equally critical to the success of making electrical interconnections, a real-time interconnect process monitor and methods to identify the root causes of interconnection failures during, and after, the bonding process were developed. The process monitor and the techniques used to verify the establishment of interconnections are elaborated. >