Abstract: This paper presents a study of board-level interconnection requirements for highly parallel and massively parallel computing. Analytical models of the I/O bandwidth of popular interconnection networks have been developed and show that current electronic technologies are poor in supporting the necessary I/O density and bandwidth. Optical interconnects appear to offer greater potential in meeting these I/O requirements. Several possible optical implementations of interconnecting a network of electronic processors are compared. The use of polymer waveguides appears to offer the best solution compatible with existing multiboard system architectures.

Abstract: A backplane, provides a physical layer level interconnection between a plurality of modules. The backplane includes a physical layer inplementation of an interconnection topology incorporated within one or more integrated circuits called interconnect chips. Incorporated on the interconnect chips are interconnect drivers and interconnect receivers for the physical layer implementation of the interconnection topology. These interconnect drivers and interconnect receivers provide point-to-point links between the physical layer implementation of the interconnection topology and the plurality of modules. Each point-to-point link may include two separate point-to-point link lines, one for an interconnect driver and one for an interconnect receiver. For the bus interconnection topology, alternately, each point-to-point link may be tri-level, including only a single point-to-point link line. The interconnection topology may be, for example, a bus topology, a ring topology or a circuit switched topology.

Abstract: The interconnection costs of electronically linked objects is minimized by the successive partitioning of the initial logic design. The partitioning is based upon the electrical properties of the drivers and loads of the linked objects forming the design. Further, time critical connections are weighted so as to further minimize interconnection cost. A further method refines the result of the successive partitioning by calculating each linked object's contribution to the overall delay of the design. Both the design of device function and timing and the physical realization of the electronically linked objects are solved jointly to make use of the information available from the logical and physical designs.

Abstract: The layer assignment problem that arises in the design of a multichip module, a high-performance compact package for the interconnection of several hundred chips, is studied. The aim is to place each net in a x-y pair of layers, so as to minimize the number of such pairs. An approximation algorithm, running in O(nd) time is presented for minimizing the number of layers, where n is the number of nets and d is the (two-dimensional) density of the problem. >

Abstract: A silicon-based laser mounting structure is disclosed which provides improved interconnection between a semiconductor optical device, such as a laser, and an external high frequency modulation current source, by reducing the presence of parasitic inductive elements in the interconnecting network. The structure includes a stripline transmission path formed by depositing metal conductive strips on the top and bottom surfaces of a silicon substrate. The conductive strips are coupled at one end to the external modulation current source. A thin film resistor is deposited between the second end of the top conductive strip and the semiconductor optical device. This thin film resistor is utilized to provide impedance matching between the optical device and the stripline. That is, for a laser with an impedance ZL, and a stripline designed to have an impedance ZS, the resistance R is chosen such that R+ZL =ZS. Utilizing silicon processing techniques, the thin film resistor may be placed adjacent to the laser, reducing the parasitics associated with their interconnection. A conductive via is formed through the substrate to provide a top-side bonding location for connecting the optical device to the bottom metal conductor by providing the top-side site, the parasitic inductance associated with this interconnection is considerably reduced.

Abstract: A packet parallel interconnection network for routing packets in parallel form comprises a three-dimensional space domain switch which interconnects a plurality of time domain switches in the form of multiple two level bus systems with separate data and control paths. The space domain switch comprises one control plane and a plurality of data switching planes such that the i th data switching plane routes the i th data slice of a packet. The control plane and the data switching planes comprise output buffered crosspoint switches. The control plane processes address information in the packets to be routed and broadcasts routing information to the data switching planes to control the routing of data slices by the data switching planes. It is a significant advantage of the time and space domain switches that decoupled control and data paths provide for overlapped control processing and data routing. The inventive interconnection network is especially useful for implementing a parallel processing system for processing database queries.

Abstract: A flip-chip interconnection technique using small solder bumps instead of conventional wire bonding for high-speed broadband photoreceivers is described. The technique achieves interconnection with low parasitic elements, no damage to devices, and easy assembly. A photoreceiver composed of a broadband p-i-n photodiode and a laser-speed GaAS metal-semiconductor field-effect transistor (MESFET) preamplifier connected using solder bumps that are about 26 mu m in diameter, with a frequency response of over 22 GHz at 1.55 mu m, is demonstrated. This confirms the effectiveness of the solder bump interconnection technique for future high-speed broadband optical modules. >

Abstract: A timing-driven global router is presented for custom chip design, whose objective is maximizing the minimum delay slack. Resistances and capacitances of interconnections, input gate capacitances and output driver resistance are used to approximate the interconnection delays during the routing. The router incrementally updates the delay at each sink pin of the signal obtained from the previous step during the routing. The maximum allowable delay at each sink pin (from a timing analyzer) along with the computed interconnection delays is used to guide the search process for the maximum-delay-slack route. It is shown that when the interconnection resistance is comparable to the output-driver resistance, minimizing the total net length is not always equivalent to minimizing the delay for a multiterminal net. The algorithm presented is experimentally shown to produce global routes achieving the objective. >

Abstract: A three-dimensional interconnection technology is described that allows a reduction of the occupied area by a factor of 7 or 8 as against 2-D interconnection. The approach consists of interconnecting the bare chips not in the XY plane, but along the Z-axis. The process entails interconnecting the four lateral areas (sides) of the cube formed by stacking n chips (n=8-10) on top of one another. The chips are individually interconnected on a thin film identical to a TAB (tape automatic bonded) film by means of gold wires, prior to cubing. These chips are standard, off-the-shelf, bump-free devices. After passing electrical testing and burn-in, they are then glued on top of one another with the TAB film. After these n chip+film assemblies have been cured (polymerized), a trim operation is carried out to cut the n-chips cube out of the TAB-film carrier cube. The trim line is approximately 100 mu m from the edge of the chips. The cube containing the n chips thus provides four lateral areas (sides) in which appear the cross sections of the gold wires connecting each lead of each chip to the corresponding leads on the flexible films. These gold wire cross-sections may be interconnected in two different ways according to the number of chip layouts/outputs or the conductor pitch. >

Abstract: As integrated circuit linewidths are reduced, single chip system functionality and speed increase. Conventional electronic chip input/output does not scale with this trend: bonding pad sizes and off-chip capacitive loads remain essentially constant. The shortage of chip interconnect capability has become critical. Integrated free-space optical interconnect has the potential to overcome this problem by providing a large number of high speed connections between chips. This paper describes methods for performing free-space intermodule optical interconnections within a digital electronic computer utilizing large arrays of light beams. A particular architecture and its ongoing implementation with integrated components are discussed.

Abstract: The results of an investigation exploring the feasibility of laser-drilled microvias are reported. The process relies on the use of a single pulses from a CO/sub 2/ laser to drill small holes in panels of epoxy-glass. It is suitable for the generation of both buried and blind vias. Stop-and-go and on-the-fly drilling methods were examined. To test the quality of laser-drilled holes, daisy-chain patterns including these holes were fabricated using conventional subtractive technology. These patterns were subjected to successive thermal shocks to detect connection failure via resistance changes. The specimens tested showed no degradation when certain metallization procedures were followed. Other samples were subjected to reliability testing and compared to mechanically drilled vias. No statistical difference between the two groups could be established. Based upon these results, a production-type laser system was constructed capable of drilling sub-0.004-in-diameter holes over 18 in*24 in panels at rates of up to several hundred holes per second. High resolution and a high absolute accuracy were achieved. A description of the system is provided. >

Abstract: A display device with LEDs includes an interconnection frame in which an electrical lead interconnection is formed by conductive metal plating on a surface including a main surface of a resin substrate capable of receiving a plating process. LEDs are bonded at the predetermined positions on the main surface of this interconnection frame so that they are connected to the electric lead interconnection. A reflection case having openings with their inner peripheral surfaces serving as reflection surfaces surrounding the LEDs is affixed to the main surface of the interconnection frame at a position corresponding to the LED arrangement. In the openings of the reflection case, the LEDs are covered with light transmissive resin members. Because the interconnection frame for the lead is formed of resin as well as the reflection case and provided with metal plating interconnection, thermal stresses are not produced due to difference of thermal expansion coefficient between the interconnection frame and the reflection case.

Abstract: We present an algorithm for optical interconnection of two-dimensional arrays by transmitting the input through a phase-code mask then correlating it with a control image constructed from the interconnection weights. An arbitrary complex-weighted interconnection pattern can be encoded. We show how the output signal-to-noise ratio can be traded for control image size and complexity by adjusting the phase-code feature size. Theoretical calculations of the average output signal-to-noise ratio are compared with computer simulations of the algorithm.

Abstract: The LSI packaging technique utilized for the SX-3/SX-X is outlined. The VLSI chip is packaged in a chip carrier called the flipped tape-automated-bonding carrier (FTC), which has 604 input/output (I/O) bumps arranged in a matrix configuration on its bottom surface. The high-density multichip package (MCP) consists of a multilayer substrate (MLS) with a maximum of 100 FTCs and 11540 I/O pins. The MLS is a 225-mm*225-mm, 5.5-mm-thick ceramic substrate with a fine-line multilayer wiring part consisting of seven polyimide insulative layers and eight conductor layers. A multilayer board mounts the MCPs with novel zero insertion force (ZIF) connectors, and high-speed coaxial cablings are used for the interconnection system. Adoption of the ZIF-MCP connector allows insertion of multiple pin sat one stroke and high-speed interconnection. A sophisticated and reliable water cooling technique is used to cool the package efficiently. Water circulates from a cooling unit (CLU) to liquid cooling modules (LCM) that cover the MCPs. This system has a cooling capacity of up to 4-kW heat dissipation of the MCP. >

Abstract: One of the more promising interconnection schemes proposed for use in photonic switching networks is the crossover interconnection network; however, reported implementations of the crossover have been limited in size and complexity. A large-scale cascadable implementation of the optical crossover network that capitalizes on planar symmetric self electrooptic effect device (S-SEED) arrays is discussed. A fully functional experimental prototype with 32 inputs and 32 outputs that was operated at a maximum rate of 55.7 kb/s is also discussed. It is also shown that S-SEED arrays can be operated as simple two-input two-output nodes (called 2-modules) within a controllable network. >

Abstract: A comprehensive network management function built into the interconnection network provides a means of meeting user needs of fault tolerance, performance, accounting, and security. However, meeting these needs on a heterogeneous interconnection network is several levels more complex than on a homogeneous network because of the existence of multiple protocol stacks for communication. An architecture that will solve this problem by analyzing the heterogeneous interconnection network as a single entity is proposed. The authors present the design issues evaluated in choosing this approach and establish the need for the various components in this architecture. An overview is presented of each of the components, and their place in the architecture is pointed out. >

Abstract: Multiprocessors require an interconnection network to connect processors with memory modules. The performance of the interconnection network can have a large effect upon overall system performance, and, therefore, methods are needed to model and compare alternative network architectures.This paper is concerned with evaluating the performance of multistage interconnection networks consisting of k × s switching elements. Examples of such networks include omega, binary n-cube and baseline networks. We consider clocked, packet switched networks with buffers at switch output ports. An analytical model based on approximate Mean Value Analysis is developed, then validated through simulations.

Abstract: Chip mounting methods, chip-substrate interconnection techniques, encapsulation processes, design methods and technologies for multi-chip systems must all be considered in microelectronic packaging. In the case of sensors, as well as the electrical contacts for signal outputs and power distribution, the input of the non-electrical measurement signals must be realized. Parts of the sensor are therefore in direct contact with environmental physical and chemical parameters which can degrade the reliability. Therefore the requirements for sensor packaging technologies are related to specific measurement problems. In general, sensor packaging has to deliver reliable, economical and application-oriented solutions by choosing optimal technologies and material combinations.

Abstract: A multistage interconnection network (MIN) for multiprocessor systems is proposed. The proposed MIN, called the B-network, uses backward links to provide backward paths for the requests blocked at switches or memory due to contentions. The gamma network is known to contain a cube network (specifically, the inverse omega network) as a substructure. The B-network is obtained from the gamma network by preserving the cube structure but reversing the direction of all other links. These backward links are used as alternate paths for requests blocked due to path or memory contentions. The B-network can be controlled by the simple destination tag control algorithm; packets navigating through the B-network, using both regular forward links and backward links, can reach their destinations under the destination tag control. The performance of the B-network is analyzed under the uniform traffic model and compared to various networks of interest. It is shown that the B-network surpasses the performance of the gamma network, the crossbar switch, and single-buffered MINs based on (2*2) switches, while having the same hardware complexity as the gamma network. >

Abstract: Physical delay models entirely based upon device equations for small-geometry CMOS inverters with RC tree interconnection networks are presented. Through extensive comparisons with SPICE simulation results, it is shown that the maximum relative error in delay-time calculations using the developed model is within 15% for 1.5- mu m CMOS inverters with RC tree interconnection networks. An experimental sizing program is constructed for speed improvement of interconnection lines and trees. In this program, given the size of the input logic gate and its driving interconnection resistances, capacitances, and structures, users can choose one of four speed-improvement techniques and determine the suitable sizes and/or number of drivers/repeaters for a minimum delay. The four speed-improvement techniques use minimum-size repeaters and cascaded input drivers to reduce the interconnection delay. It is found that the required tapering factor in cascaded drivers is not the base of the natural logarithm, but a value in the range 4-8. Adding a small number of drivers/repeaters with large sizes reduces the interconnection delay more efficiently. >

Abstract: An overview of the present status and future trends in electronic packaging technologies is presented. Advanced modules packaged with these technologies are show in three major systems: switching systems, transmission systems, and computer systems. It is projected that high-speed digital switching modules will adopt multichip packaging because they can transmit high-speed pulses. In the latter half of the 90s, prototypes of optical switching modules will be implemented. In optical communication systems, a fine flip-chip interconnection technique using solder bumps will become indispensable for high-speed optical modules operating at over 20 GHz. As inductance corresponding to wire length degrades electrical characteristics, innovative packaging using impedance-matched film carriers will be developed for GaAs MMIC (microwave monolithic integrated circuit) modules in future microwave transmission systems. Multichip packaging will be widely used in computer systems because it provides higher packaging density, ensuring reduced interconnection delays. >

Abstract: A simple and efficient board-to-board optical interconnection consisting of only a laser, two lenses, and a detector demonstrates the direct free-space interconnection of digital circuits. No external laser driver, detector preamplifier, or other interface circuitry was required because of the high efficiency of the link. A differential electrical-to-electrical current efficiency as high as 19% was measured. The interconnection operates at clock rates of 1 GHz.

Abstract: An architecture of an all-optical multistage interconnection network is proposed. The network supports a circuit-switching model of communication and can provide parallel optical paths among input and output ports. It uses an address-based routing algorithm for path setup which, due to its decentralized nature, makes this network suitable for designing high-speed switching systems. These switches are commonly used in telephony and multiprocessor systems. The proposed architecture uses bistable optical devices, such as interference filters, as essential components of its switching modules. Since these devices can be easily fabricated, the implementation of this architecture is feasible. Various design issues related to optical clock generation, its distribution, data synchronization, and intensity restoration are also discussed. >

Abstract: In a focal plane array sensor hybrid, a focal plane array fabricated in a chip of one semiconductor material and a read out circuit fabricated in one or more chips of a different semiconductor material are connected by a high density interconnect structure in which a layer of dielectric material is bonded to the chips and has interconnecting conductors disposed thereon and extending through via holes therein into ohmic contact with appropriate contact pads of the chips. Inclusion of a flexible portion in the high density interconnect structure enables the readout and the focal plane array chips to be disposed in different planes to provide a compact structure. Focal plane array sensor hybrid testing and repair are both facilitated by this structure.

Abstract: The problems of gossiping and broadcasting in one-way communication mode are considered for some prominent families of graphs. The complexity is measured as the number of communication rounds in the gossip and broadcast algorithms. The main result of the paper is the precise estimation of the gossip problem complexity in cycles. To obtain this result a new combinatorial analysis of gossiping in cycles is developed. This analysis leads to an optimal lower bound on the number of rounds, and also to the design of an optimal algorithm for gossiping in cycles. The optimal algorithm for gossiping is later used to design new, eeective algorithms for gossiping in important families of interconnection networks (cube connected cycles; butterf ly networks). Further, a new, eeective algorithm for broadcasting in Shuue-Exchange networks is developed.

Abstract: The exact structural relationship between the hypercube and multistage interconnection networks for multiprocessors is characterized here. By varying the node architecture, structures other than these two interconnection schemes can be derived.

Abstract: An approach which reduces the number of pads required by electrical test structures is presented. The multiplexed scheme requires only two levels of interconnect and enables more devices to be located in a given area, providing the designer of test structures with more freedom to experiment with structures previously requiring a large number of pads. Applications for transistors, electrical verniers, yield monitoring, reliability evaluations, continuity tests, and measuring the resistance of tracks are discussed. >