Abstract: Our methodology for the abstract specification of (classes of) objects parallels traditional algebraic ADT specifications in many ways. We believe that our approach clarifies the essential difference between data abstraction and object abstraction. It stresses the connection of the behavior of objects with sequences of messages while maintaining the essence of state as an overt but completely abstract entity. While we abstract away from details about state, we do not regard it as a hidden sort as in [GM87] — the presence or absence of state is not transparent. Effective integration of the state concept into formal specification enhances an intuitively natural match of the abstraction with implementation details. The idea of viewing state as a hidden argument captures intuition better since its connection with the visible operations is concealed but not completely severed. The approach we suggest begins with categorizing the methods according to their dependence and effect on the internal state of an object and making those categories an explicit part of the specification. Specifications of the state transition functions are associated with the side-effect inducing methods and provide an abstract description of each of them and the states. Once the state behavior is established, descriptions of the state-dependent methods can be pursued. Because of the role of states in overall behavior, our specifications are intended to distinguish objects only if they have observable behavior which differs. Thus we prefer the final algebra interpretation [GH78, Kam83, Wan79] over the initial algebra view [GTW78]. Of course, the state-independent methods constitute an ordinary ADT and can be specified by well established means. We wish to describe object behavior and hence seek to avoid differentiation of objects based on their internal structure. Hence two states are equivalent (indistinguishable) provided that if we start with two objects, one in each of these states, then for every sequence of messages ending with a selector message, both objects return the same result — that is, the two objects are indistinguishable by any external means. In the ADT literature this is known as the " final algebra " view. Since our approach results in an ADT-style description of a collection of functions, ADT analysis concepts generally apply. For instance, " sufficient completeness " for terms whose primary operation is a selector remains a property of interest. The primary difference to be accounted for is with the State domain which is represented by sequences of side-effect …

Abstract: Effect of scaling of dimensions, i.e., increase in chip size and decrease in minimum feature size, on the RC time delay associated with interconnections in VLSIC's has been investigated. Analytical expressions have been developed to relate this time delay to various elements of technology, i.e., interconnection material, minimum feature size, chip area, length of the interconnect, etc. Empirical expressions to predict the trends of the technological elements as a function of chronological time have been developed. Calculations of time delay for interconnections made of poly-Si, WSi/sub 2/, W, and Al have been done and they indicate that as the chip area is increased and other device-related dimensions are decreased the interconnection time delay becomes significant compared to the device time delay and in extreme cases dominates the chip performance.

Abstract: Using a simple finite degree interconnection network among n processors and a straightforward randomized algorithm for packet delivery, it is possible to deliver a set of n packets travelling to unique targets from unique sources in 0(log n) expected time. The expected delivery time is in other words the depth of the interconnection graph. The b -way shufile networks are examples of such.This represents a crude analysis of the transient response to a sudden but very uniform request load on the network. Variations in the uniformity of the load are also considered. Consider si packets with randomly chosen targets beginning at a source labelled i. The expected overall delay is then [equation] where the labelling is chosen so that s1≥s2≥.These ideas can be used to guage the asymptotic efficiency of various synchronous parallel algorithms which use such a randomized communications system. The only important assumption is that variations in the physical transmission time along any connection link are negligible in comparison to the amount of work done at a processor.

Abstract: The Gamma network is an interconnection network connecting N=2' inputs to N outputs. It consists of log2N stages with N switches per stage, each of which is a 3 input, 3 output crossbar. The stages are linked via “power of two” and identity connections in such a way that redundant paths exist between the input and output terminals. In this network, a path from a source to a destination may be represented using one of the redundant forms of the difference between the source and destination numbers. The redundancy in paths may thus be studied using the theory of redundant number systems. Results are obtained on the distribution of paths connecting inputs to outputs, and the permuting capabilities of the Gamma network. Switch settings for certain frequently used permutations and control mechanisms are also considered in this paper. This network has an interesting application in solving tridiagonal systems using the odd-even elimination algorithm.

Abstract: Multiple processor interconnection networks can be characterized as having N' inputs and N' outputs, each being B' bits wide. A major implementation constraint of large networks in the VLSI environment is the number of pins available on a chip, Np. Construction of large networks requires partitioning of the N' * N' * B' network into a collection of N * N switch modules with each input and output port being B (B ≤ B') bits wide. If each module corresponds to a single chip, then a large network can be implemented by interconnecting the chips in a particular manner. This correspondence presents a methodology for selecting the optimum values of N and B given values of N', B', Np, and the number of control lines per port. Models for both banyan and crossbar networks are developed and arrangements yielding minimum: 1) number of chips, 2) average delay through the network, and 3) product of number of chips and delay, are presented.

Abstract: Interconnection capacitances and inductances on oxide-passivated silicon, sapphire, and semi-insulating gallium arsenide substrates were calculated and compared. The results showed that, including coupling effects, the capacitances on insulating substrates are lower only at large linewidths, but become comparable to values on silicon substrates at linewidths below 2.5 µm. The frequency-dependent nature of inductances on silicon substrates was reviewed. The results indicated that, at frequencies where most digital integrated circuits operate, silicon substrates can be treated as a lossless medium. Hence, inductances on silicon substrates can be calculated by the same means as on insulating substrates. The propagation delay of an interconnection resulting from using different substrates was also evaluated. It can be shown that for VLSI development the choice of substrates is not nearly as critical as the problem of series resistance of an interconnection.

Abstract: A plug-in interconnection for optical and avioptic cables for connecting those cables into equipment such as circuit boards having fiber optic circuitry running in a plane normal to the axis of the plug-in interconnection. In the interconnection, a male connector having the end of the optical fiber means of the cable projecting from the end thereof is plugged into an on-axis female receptacle. In the receptacle, an aperture normal to its axis receives either the end or light from the end of the optical fiber circuit means in the equipment being interconnected. Reflecting means in the bore of the female receptacle aligned with the axis of optical fiber means in the male plug-in connector, when plugged in, reflects light signals between the optical fiber means in the connector and the circuit means in the equipment. An embodiment in which the light signal reflecting means is in the male connector is also disclosed. The interconnection can incorporate electrical termination means such as to provide a combined optical and electrical plug-in connector.

Abstract: A central issue in the design of multiprocessor systems is the interconnection network which provides communications paths between the processors. For large systems, high bandwidth interconnection networks will require numerous 'network chips' with each chip implementing some subnetwork of the original larger network. Modularity and growth are important properties for such networks since multiprocessor systems may vary in size. This paper is concerned with the question of timing control of such networks. Two approaches, asynchronous and clocked, are used in the design of a basic network switching module. The modules and the approaches are then modelled and equations for network time delay are developed. These equations form the basis for a comparison between the two approaches. The importance of clock distribution strategies and clock skew is quantified, and a network clock distribution scheme which guarantees equal length clock paths is presented.

Abstract: A flexible area-bonding tape (2) comprising a flexible, electrically insulating body, and arrays of internal and external terminals (10 and 11) which are electrically interconnected by multiplicities of conductive paths (14). At least some of the paths (14) are essentially completely embedded in the body.

Abstract: Interconnection capacitances and inductances on oxide-passivated silicon, sapphire, and semi-insulating gallium arsenide substrates were calculated and compared. The results showed that, including coupling effects, the capacitances on insulating substrates are lower only at large Iinewidths, but become comparable to values on silicon substrates at linewidths below 2.5 /spl mu/m. The frequency-dependent nature of inductances on silicon substrates was reviewed. The results indicated that, at frequencies where most digital integrated circuits operate, silicon substrates can be treated as a lossless medium. Hence, inductances on silicon substrates can be calculated by the same means as on insulating substrates. The propagation delay of an interconnection resulting from using different substrates was also evaluated. It can be shown that for VLSI development the choice of substrates is not nearly as critical as the problem of series resistance of an interconnection.

Abstract: This circuit system accommodates the interconnection of a plurality of modules, each containing a plurality of semiconductor chips, by means of a flexible printed circuit wiring assembly containing contact pads and an interconnection wiring pattern. The modules contain a set of contact pads corresponding to the pads on the flexible wiring assembly and alignment pins to bring the abutting pads into registration. The pads on the flexible wiring assembly have a plurality of contact bumps to make better contact with the module packs. Clamping means is provided to retain the module and exert pressure on the contact pads.

Abstract: Brake power control units for two-circuit brake systems are known in which a control piston and a locking piston are provided. The control piston reduces the brake pressure of the rear axle brake circuit in relation to the brake pressure of the front axle brake circuit and the locking piston acts on the control valve in the case of failure of the front axle brake circuit in such a way that the reducing effect for the rear axle brake pressure is neutralized. The two pistons of this known unit are arranged one behind the other which requires a great overall length for the control unit. According to the present invention, the overall length of the control unit is reduced by disposing the two pistons coaxial with respect to each other with the control piston enclosing the locking piston.

Abstract: A new class of general topologies is proposed in this paper for interconnecting a large network of computers in parallel and distributed environment. These structures have been shown to possess small internode distances, fairly low number of links per node, easy message routing and large number of alternate paths that can be used in case of faults in the system. The interconnection is based on a mixed radix number system, presented in this paper. The technique results in a variety of structures for a given number of processors N, depending on the required diameter in the network.A bus oriented structure is also introduced here, based on the same mathematical framework. These structures possess only two I/O ports per processor and are also shown to have small internode distances.

Abstract: We propose an efficient and simple optical interconnection between active semiconductor components by deposition and spin coating. The demonstration shows a low-threshold (2.0 kA/cm2) and high-coupling (81%) operation of a laser-polyimide/SiO2 slab waveguide integrated on a GaInAsP/InP chip.

Abstract: A semiconductor integrated circuit in which layers such as an field isolation region, a gate electrode, interlayer insulating films and interconnection lines are formed by the combined use of a lift-off process and an ECR plasma deposition process. According to the present invention, even if vertical dimensions of patterns of the respective layers are large as compared with their lateral dimensions, the upper surfaces of the respective layers can be planarized, permitting the fabrication of an LSI of high packing density, high operating speed and high reliability which is free from shorting and breakage of the interconnection lines.

Abstract: By use of a double-exposed (double-etch) low temperature polyimide/oxide process, the packing density for both first and second level metal interconnection can be improved by some 35 percent and 30 percent, respectively, in the vicinity Of the via. Moreover, the complete interconnect process may be realized at temperatures below 300°C. Since polyimide can be applied in thick layers having negligible (tensile) stress, a planar surface results and also parasitic lead capacitances may be considerably reduced. This process is also amenable to either wet chemical or dry plasma processing.

Abstract: The present disclosure describes a universal leadless chip carrier mounting pad layout for an interconnection medium such as a printed circuit board, which accommodates a wide range of chip carrier sizes. Thus, there is eliminated the traditional method of providing custom pad layouts homologously configured as to numbers of pads and their arrangement, in specific chip carriers. The universality of the present pad layout makes it especially desirable for prototype designs, and integrated circuit chip "burn in" and test procedures.

Abstract: A semiconductor device for use in an optical device and a method of manufacturing the same are disclosed. The device comprises a plurality of active cells and a plurality of wiring cells. The resistors formed in the device are constituted by combining these wiring cells.

Abstract: This paper reports the results of recent efforts to characterize the frequency on the Eastern Interconnection. The power system line frequency has been used routinely in the control and management of generation. A data collection and analysis program was undertaken to enable the characterization of this line frequency over time spans from five minutes to twenty-four hours. The results shown here reveal the range of frequencies that appear on the Interconnection, the nature of the variation about the 60 Hz set point, the spectrum of periodic components present, and the influence on the measured frequency of the averaging time used for measurement.

Abstract: A method of manufacturing a mask type read only memory having an interconnection wiring and a plurality of MOS transistors, wherein selected source and drain regions are shortened in accordance with a user program after the interconnection wiring layer is formed on the semiconductor substrate. After that, a protective film is formed over the entire surface of the read only memory.

Abstract: In a semiconductor device having a gate array structure, a macro-cell includes more basic cells than conventional macro-cells, for preforming a logic function, whereby the density of the terminals in a direction vertical to a direction in which wiring lines are drawn, is decreased.

Abstract: We propose an efficient and simple optical interconnection between active semiconductor components by deposition and spin coating. Details of the waveguide design, the fabrication technique, and a promising material combination are given. Experimental results with an integrated laser-polyimide/SiO x ( x \sim 2 ) waveguide combination demonstrate low-threshold (2.0 kA/cm2) laser operation and a low-loss waveguide interconnection (81 percent coupling efficiency) on a GaInAsP/InP chip.

Abstract: The application of multilevel control strategies for load-frequency control of interconnected power systems is assuming importance. A large multiarea power system may be viewed as an interconnection of several lower-order subsystems, with possible change of interconnection pattern during operation. The solution of the control problem involves the design of a set of local optimal controllers for the individual areas, in a completely decentralised environment, plus a global controller to provide the corrective signal to account for interconnection effects. A global controller, based on the least-square-error principle suggested by Siljak and Sundareshan, has been applied for the LFC problem. A more recent work utilises certain possible beneficial aspects of interconnection to permit more desirable system performances. The paper reports the application of the latter strategy to LFC of a two-area power system. The power-system model studied includes the effects of excitation system and governor controls. A comparison of the two strategies is also made.