Abstract: A semiconductor device including a double cavity semiconductor chip carrier (100) which comprises a multilayer ceramic sandwich structure having a pair of semiconductor chip receiving cavities in the opposite faces thereof. The package enables mounting and electrical interconnection of a pair of semiconductor integrated circuit chips in a package of the same size as that for a single chip and having somewhat greater thickness. External terminals (93) on an outside face of the carrier are connected selectively by metallization paths (44, 53, 55, 83) integral with the carrier to chip mounting pads (41, 51) and to internal terminals (28) within the carrier. The internal terminals are disposed peripherally with respect to the chip cavities and adapted for interconnection with chip contact pads (26). Thus, a pair of unlike semiconductor integrated circuits can be interconnected in accordance with different patterns within a single package.

Abstract: The cube network can support both MIMD and SIMD processing in distributed systems. It allows flexible communications in systems like PASM, PUMPS, and the BMD test bed.

Abstract: A chip carrier having a plurality of leads thereon for external interconnection with preferably only one of the leads utilized to provide a source of power to the chip and preferably a single lead utilized as a ground connection. The power and ground leads are connected in a bus structure around the chip at the center of the chip carrier with the chip being secured to the chip carrier with the bus structure over a thermal pad formed within the bus structure. A decoupling capacitor is located in close proximity to the chip on the substrate to assure low reaction due to switching.

Abstract: Adding buffers to a packet switching network can increase throughput in certain system architectures. A word of warning—don't make them too large.

Abstract: In a high speed automatic fine wire bonding machine of the type adapted to produce a wire interconnection between two bonding points on a semiconductor device there is provided a method of making consistent, exact predetermined lengths of wire under the working face of a bonding tool after a second bond is finished and in preparation for making the next first bond of a wire interconnection.

Abstract: An electric heater plate is disclosed which is formed on one surface of a base material. A plurality of thin lines of a nonprecious material which acts as a resistor when electrical energy flows therethrough is bonded to the first surface of the base material and extends from a first location thereon to a second location thereon. At least two interconnection areas of a non-precious metal which acts as a resistor when electrical energy flows therethrough are provided. These interconnection areas are bonded to the first surface of the base material with one interconnection area interconnecting the plurality of thin lines at the first location and the second of the interconnection areas interconnecting the plurality of thin lines at the second location on the first surface of the base material. A termination area of silver ceramic material is associated with each of the interconnection areas. Each of the terminal areas is in contact with an associated interconnection area. An electrical lead is bonded to each of the terminal areas for making electrical connection to the plurality of thin lines. If the electric heater plate is installed as the rear window of a motor vehicle, the heat generated by flowing the current through the thin lines can defog and deice the window.

Abstract: Networking techniques allow several processors within a multiprocessing system to cooperate efficiently on a single large problem.

Abstract: This paper presents a cluster structure, characterized by a set of structure parameters and a set of interconnection functions, as a conceptual interconnection scheme for large multimicrocomputer systems. It is shown that three popular interconnection structures (hypercube, hierarchy, and tree structures) are examples of the cluster structure. Two communication problems (traffic congestion and message delay), which may result in interconnection limitation to a particular structure, are analyzed. The analysis provides a way to understand structural properties such as complexity, capacity, and limitation. Through the use of the cluster structure and the analytical model, topological optimization is presented to show how interconnection limitation can be minimized.

Abstract: An electronic circuit interconnection system provides high density mounting of ceramic chip-carrier integrated circuit devices or other beam-lead, dual-in-line (DIP), tape- automated-bonded (TAB), flip-chip, or direct-mounted i.c. devices with wire-bonded interconnects or the like on an economical, dimensionally-stable, interconnection substrate which has high heat dissipating properties. The substrate has glass components which are fused onto etched metal patterns and which are proportioned relative to the metal patterns so that the heat-expansion properties of the substrate correspond to those of the i.c. devices to maintain bond integrity between the i.e. leads and circuit paths on the substrate and so that the substrate has sufficient heat-dissipating properties to permit the high density i.e. mounting. The substrates incorporate circuit paths, device mounting pads, edge terminals, pin mounting holes and other typical substrate features in the etched patterns in multi- metal laminated metal plates of selected thickness which are coated on one or both sides with glass frit fused to the plates. Where substrates with more than one layer are desired, glass-coated plates are stacked with pin mounting holes and the like aligned and the glass coatings are fused together. Metal vias extend through the glass coatings where desired to interconnect metal layers of the substrate.

Abstract: A chip carrier having a plurality of leads thereon for external interconnection with preferably only one of the leads utilized to provide a source of power to the chip and preferably a single lead utilized as a ground connection. The power and ground leads are connected to an interdigitated lead array at the center of the chip carrier with the chip being secured to the chip carrier above the interdigitated pattern. The chip is bonded to a dielectric sliver which rests above a glass filler and bonding agent which fills the space between the interdigitated pattern and the sliver. The chip is hermetically sealed within the ceramic cap which is bonded to the chip carrier. Power and ground connections are made, from the chip directly to a pair of buses surrounding the interdigitated pattern rather than to leads extending outwardly to the edge of the chip carrier.

Abstract: A method for providing high density multiple level metallurgy for integrated circuit devices in which a relatively thin layer of plasma produced silicon nitride is deposited over a first level of interconnection metallurgy formed on a layer of silicon oxide. Overlap via holes are etched in the nitride layer followed by deposition of a thicker layer of polyimide forming polymer. A second set of via holes larger than the first are provided in the polymer layer and a second layer of interconnection metallurgy is then deposited by a lift-off deposition technique.

Abstract: A system for connecting a semiconductor chip carrier to a printed circuit card is described. The semiconductor chip carrier has a flexible, extendable wiring membrane attached to the bottom thereof which extends beyond the periphery of the semiconductor chip carrier and in the area beyond the periphery is provided with electrical contacts. The electrical contacts are mated to complementary contacts in a printed circuit card which is biased from the semiconductor chip carrier by electrical and thermal contact means. The membrane, inter alia, provides high density electrical contact between the semiconductor and printed circuit card. Various elements thereof and a process for forming the same are described.

Abstract: An interconnection circuitry for two local area contention networks which is adapted to jam the respective networks when stations on both sides of the interconnection circuitry attempt transmission. If stations on opposite sides of the interconnect circuitry begin transmitting at the same time, the interconnect circuitry operates to place a high signal on the channel of each network and all stations will detect that the data is garbled and discard it.

Abstract: Although VLSI MOSFET devices have small inherent delays, the RC time constant of the interconnections limits the circuit maximum frequency of operation. A circuit-based solution to this problem, rather than a technology-based solution, is to use circuit configurations that maximize the charging/discharging currents delivered to the interconnections. This paper examines the different MOSFET circuit configurations based on the ability to charge/discharge the RCs of the interconnections and concludes that two circuit configurations are most suitable for VLSI: CMOS and a proposed current steering NMOS. In the latter configuration, the distributed RC network of the interconnection is included in a charging/discharging circuit path which is part of a difference stage. A multisource MOSFET structure is used in the design of the difference stage, in a common-drain/common-gate configuration to maximize the charging/discharging currents. Computer simulation using SPICE 2 and experimental measurements are used to confirm the predicted performance.

Abstract: A first semiconductor circuit element including a first electrode is formed on a semiconductor substrate, an inter-layer insulating layer for insulating the first electrode is formed on the first electrode, and a first penetrating opening is provided in a part of the inter-layer insulating layer. Subsequently, a step of forming a second semiconductor circuit element is carried out, this step including a step of forming a second electrode so that at least a part thereof may overlie the inter-layer insulating layer at an area other than the first penetrating opening. Further, a subsidiary interconnection conductive layer is buried into the first opening. Another insulating layer is formed on the structure thus formed, whereupon second and third penetrating openings are respectively provided in the insulating layer over the second electrode and the interconnection subsidiary conductive layer. First and second interconnection conductors are respectively buried into the second and third penetrating openings. The first electrode is conductively connected with the second interconnection conductor in the third opening via the subsidiary interconnection conductive layer in the first opening. The second electrode is conductively connected with the first interconnection conductor in the second opening.

Abstract: A first level interconnection layer of substantially a given width is formed on an insulating film on a semiconductor substrate. At least two second level interconnection layers, which cross the first level interconnection layer on another insulating layer, are formed. In a step for forming the first level interconnection layer, projections are formed at each side of the first level interconnection layer between the crossings of the second level interconnection layers. The total width of the first level interconnection layer including the width of the projection is larger than the given width. After the second level interconnection layers are formed, the projections of the first level interconnection layer are removed along with any second level interconnection layer material remaining intermediate the second level interconnection layers, thereby to prevent short-circuiting between the second level interconnection layers.

Abstract: CURRENT integrated circuit technology is making feasible computer systems consisting of hundreds or thousands of processors. One of the most difficult problems in the design of large-scale parallel and distributed computer systems is the choice of a communications network. An efficient method is needed for linking the system's processors, memories, and other devices to each other. As can be observed from the papers in this Special Issue, there are many different approaches to the solution of this problem. The best "solution" for a particular system is a function of the system's intended applications, size, speed requirements, cost constraints, etc.

Abstract: This paper describes a placement method of rectangular blocks with the interconnection channels. The method consists of a constructive initial placement followed by an iterative improvement. An estimation of the interconnection channel widths, the number of crossovers and the connection lengths is proposed. The criteria to be minimized are : area, number of crossovers and connection length.

Abstract: : Parallel computer architecture complicates the already difficult task of parallel programming in many ways, e.g., by a rigid interconnection structure, addressing complexity, and the shape and size mismatches. The CHiP computer is a new architecture that reduces these complications by permitting the processor interconnection structure to be programmed. This new kind of programming is explained. Algorithms are presented for several interconnection patterns including the torus and the complete binary tree and general embedding strategies are identified. (Author)

Abstract: The high resistance of diffused electrical interconnection lines used for ground return paths in MOS field effect transistor (MOSFET) arrays limits their size and performance. Advantage is taken of the extra interconnection level available from conventional double-layer-polycrystalline silicon (polysilicon) processes to distribute ground potential to arrays, by means of a polycrystalline grid with direct contact to diffused electrodes therein, thus greatly reducing the deleterious effects of ground resistance. The proposed ground grid is integrated into the structure of a MOSFET ROM using a typical double polysilicon process. The first polysilicon level provides the conductive medium for said ground grid and the diffusing doping impurities that form contiguous source electrodes for the array MOSFETs. Gate electrodes thereof and word lines are formed out of the second polysilicon level. Drain electrodes are diffused and contacted by metallized output lines.

Abstract: In the course of manufacturing a wafer-scale integrated circuit, the metalization for interconnection both within each cell and between cells is achieved by the etching of a single metal layer, photoresist being deposited on the layer and exposed using a step-and-repeat mask for those areas within each cell and using a whole-wafer reticle mask for the areas of interconnection between the cells.

Abstract: Progress in patterning technologies and computer-aided circuit designs have brought us to the threshold of very-large-scale integrated (VLSI) circuits with 100 000 or more devices to be integrated on a silicon chip. In this paper we review thin film applications in the fabrication of contacts and interconnects for VLSI circuits. Device structures suitable for both bipolar and metal/oxide/semiconductor (MOS) VLSI circuit applications tend to have shallow junction depths and contact areas (silicon-metal interfaces) in the 0.2–0.5 µm and 1–2µm2 ranges respectively; also some of the circuits require Schottky barrier diodes. Consumption of silicon in the contact windows needs to be minimized with the use of silicide layers for siliconmetal contacts. The formation and use of platinum silicide layers for bipolar applications are reviewed. Our observations indicate that the carbon and oxygen present in Czochralski-grown silicon crystals interfere in platinum silicide formationand affect the electrical characteristics of the contacts. The use of barrier layers in VLSI metallization is illustrated. The interdependence of film microstructure, electromigration-induced failures and VLSI interconnection reliability is examined. The integration of a large number of components on a VLSI chip with a single level of interconnections consumes more chip area. Long interconnection paths adversely affect circuit performance. Multilevel interconnections (conductor/insulator/conductor) offer an attractive solution to increase the packing density and circuit performance. The application of PtSi/(Ti: W)/(Al-Cu)/SiO2 /(Ti: W)/Al film layers in the fabrication of a bipolar VLSI circuit with a minimum feature size of 1.25 µm is illustrated. As the complexity of VLSI circuits continues to grow with micron size device structures, three or more levels of interconnections compatible with shallow junctions on the substrates and complex packaging technologies are required. Areas of concern and desirable features in VLSI metallization are summarized.

Abstract: Interconnection networks have extensive applications in switching and multiprocessor networks. This paper shows that nested tree designs of rearrangeable interconnection networks proposed by Joel are equivalent to the CS networks discussed in Opferman and Tsao-Wu. this paper presents a new design for a t-fault tolerant CS network. This design generally requires fewer elements then the design of Sowrirajan and Reddy. Ln addition,

Abstract: An overlay interconnection technology has been developed for GaAs microwave power FETs, using polyimide as an insulator. An output power of 1017 mW at 4.3 dB gain was achieved at 8 GHz with 27° power added efficiency from a device with a gate width of 1.2 mm. Comparison with devices without overlay interconnection and having a narrower gate width revealed no evidence for degradation in device performance attributable to the interconnection technology.