TL;DR: This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.
Abstract: Using on-chip interconnection networks in place of ad-hoc glo-bal wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules (processors, memories, peripherals, etc...) communicate by sending packets to one another over the network. The structured network wiring gives well-controlled electrical parameters that eliminate timing iterations and enable the use of high-performance circuits to reduce latency and increase bandwidth. The area overhead required to implement an on-chip network is modest, we estimate 6.6%. This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.
TL;DR: The combination of decreasing feature sizes and increasing chip sizes is leading to a communication crisis in the area of VLSI circuits and systems, and the possibility of applying optical and electrooptical technologies to such interconnection problems is investigated.
Abstract: The combination of decreasing feature sizes and increasing chip sizes is leading to a communication crisis in the area of VLSI circuits and systems. It is anticipated that the speeds of MOS circuits will soon be limited by interconnection delays, rather than gate delays. This paper investigates the possibility of applying optical and electrooptical technologies to such interconnection problems. The origins of the communication crisis are discussed. Those aspects of electrooptic technology that are applicable to the generation, routing, and detection of light at the level of chips and boards are reviewed. Algorithmic implications of interconnections are discussed, with emphasis on the definition of a hierarchy of interconnection problems from the signal-processing area having an increasing level of complexity. One potential application of optical interconnections is to the problem of clock distribution, for which a single signal must be routed to many parts of a chip or board. More complex is the problem of supplying data interconnections via optical technology. Areas in need of future research are identified.
TL;DR: It is shown that the possibilities of interconnection can be completely prescribed in a characteristic logic equation that can be used as the complete basis for development of an interconnection matrix.
Abstract: A procedure is described for developing an interconnection matrix that specifies a cascade connection of two known digraphs to form a digraph. The solution of this form of the interconnection problem can be applied to complete the process of description of a binary relation initiated by the process of partitioning on elements described in a companion paper [3]. It is assumed that the contextual relation being modeled is transitive. Based on this assumption, it is shown that the possibilities of interconnection can be completely prescribed in a characteristic logic equation. This equation can be used as the complete basis for development of an interconnection matrix. An example of its use is given. Much of the burden of structural modeling is assigned to the computer, leaving to the developer the tasks requiring substantive knowledge of the system being modeled.
TL;DR: Various network topologies and switching strategies are covered here, including interconnection networks for communication among processors and memory modules.
Abstract: Concurrent processing depends on interconnection networks for communication among processors and memory modules. Various network topologies and switching strategies are covered here.