TL;DR: A novel approach to adopt this strategy to generate test patterns for SOCs is presented, which utilizes the core processor's instruction set to test its own functionality and that of the peripheral components.
Abstract: With the rapid increase in the functionality of a single chip, the generation of high quality manufacturing tests which can be applied at-speed has become a serious issue. The problem is further compounded with an increasing level of integration in the case of Systems-On-Chip (SOCs), for which existing test generation tools are inadequate. Many of the peripherals in a SOC design may not include testability features, which renders conventional design for testability (DFT) approaches ineffective. Functional tests applied at-speed in the native mode of a microprocessor have been shown to be effective in detecting realistic defects. A novel approach to adopt this strategy to generate test patterns for SOCs is presented in this paper. This approach utilizes the core processor's instruction set to test its own functionality and that of the peripheral components. A SOC based on a model of the Intel 8085 processor is used to show the effectiveness of this approach.
TL;DR: An algebraic specification of the intel 8085 micro-processor is given, based on the concepts of hierarchical abstract types and conditional equations, which is validated against some of its informal requirements.
Abstract: As an instance for a large specification, an algebraic specification of the intel 8085 micro-processor is given. The specification is based on the concepts of hierarchical abstract types and conditional equations. With the help of the specification interpreter RAP, the specification is validated against some of its informal requirements. In the design of large software systems, a number of informal specification properties have to be considered such as style, readability, and structuredness of a specification. These properties are talked about using a couple of small examples.
TL;DR: A very small, flexible, high-quality, full-duplex 2.4-kbit/s linear predictive vocoder has been implemented with commercially available integrated circuits.
Abstract: A very small, flexible, high-quality, full-duplex 2.4-kbit/s linear predictive vocoder has been implemented with commercially available integrated circuits. This fully digital realization is based on a distributed signal processing architecture employing three Nippon Electric Company (NEC) µPD7720 signal processing interface (SPI) single-chip microcomputers. One SPI implements the LPC analyzer, a second implements the Gold pitch and voicing decision algorithm, white the third µPD7720 implements the excitation generator and synthesizer. An Intel 8085-based 8-bit microcomputer is used for data transfer, control and multiplexing functions, and communications with the host terminal. The LPC chip set achieves high flexibility by accepting run time initialization options from the Intel 8085. These parameters include choice of linear predictive model (<= 15), analysis and synthesis frame size, and speech sampling frequency, as well as choice of speech input and output coding formats (linear or µ-255 law) and choice of analog or digjtal pre- and deemphasis. A total of 16 integrated circuits is used in the LPC vocoder with a power disipation of 5.5 W and occupying 18 in/sup 2/ of circuit area.
TL;DR: In this paper, a new radiation hardened three micron CMOS process has been developed, which uses a guardbanded P-well with single level polysilicon and single level metal.
Abstract: A new radiation hardened three micron CMOS process has been developed. It uses a guardbanded P-well with single level polysilicon and single level metal. Plasma processing is used for etching the critical dimension levels of polysilicon, contact window and metal. To date, fifteen designs have been fabricated using the technology. These include CMOS equivalents of the Intel 8085 8-bit microprocessor family, two custom encryption chips of about 19,000 transistors each and custom logic designs using Sandia's standard cell family. Performance of the devices has exceeded all specifications.
TL;DR: InTRODUCTION to Microprocessor Microprocessor Data Types Microcomputer System Software and Programming Concepts Typical Microcomputer Addressing Modes and Instructions Basic Features of Microcomputer Development Systems System Development Flowchart Typical Microprocessors Typical Practical Applications Questions and Problems.
Abstract: INTRODUCTION TO MICROPROCESSORS AND MICROCOMPUTER-BASED APPLICATIONS Evolution of the Microprocessor Microprocessor Data Types Microcomputer System Software and Programming Concepts Typical Microcomputer Addressing Modes and Instructions Basic Features of Microcomputer Development Systems System Development Flowchart Typical Microprocessors Typical Practical Applications Questions and Problems INTEL 8085 Introduction Register Architecture Memory Addressing 8085 Addressing Modes 8085 Instruction Set Timing Methods 8085 Pins and Signals 8085 Instruction Timing and Execution 8085-Based System Design Questions and Problems INTEL 8086 Introduction 8086 Architecture 8086 Addressing Modes 8086 Instruction Set 8086 Assembler-Dependent Instructions ASM-86 Assembler Directives 8086 Programmed I/O 8086-Based Microcomputer 8086 Interrupt System 8086 DMA Questions and Problems INTEL 80186/80286/80386 Intel 80186 and 80286 80386 System Design Coprocessor Interface Questions and Problems MOTOROLA MC68000 Introduction 68000 Programming Model 68000 Addressing Structure 68000 Addressing Modes 68000 Instruction Set 68000 Stacks 68000 Pins and Signals 68000 System Diagram Timing Diagrams 68000 Memory Interface 68000 Programmed I/O 68000/2716/6116/6821-Based Microcomputer 68000 Interrupt I/O 68000 DMA 68000 Exception Handling Multiprocessing with the 68000 Using the TAS Instruction and as Signal Questions and Problems MOTOROLA MC68020 Introduction Programming Model Data Types, Organization, and CPU Space Cycle MC68020 Addressing Modes 68020 Instructions 68020 Advanced Instructions MC68020 Cache/Pipelined Architecture and Operation MC68020 Virtual Memory MC68020 Coprocessor Interface MC68020 Pins and Signals MC68020 Timing Diagrams Exception Processing MC68020 System Design Questions and Problems MOTOROLA MC68030/MC68040, INTEL 80486, AND PENTIUM MICROPROCESSORS Motorola MC68030 MC68040 Intel 80486 Microprocessor Intel Pentium Microprocessor Questions and Problems RISC MICROPROCESSORS: INTEL 80960, MOTOROLA MC88100, AND POWERPC Basics of RISC Intel 80960 Motorola MC88100 RISC Microprocessor IBM/Motorola PowerPC Questions and Problems PERIPHERAL INTERFACING Keyboard Interface DMA Controllers Printer Interface Coprocessors Questions and Problems DESIGN PROBLEMS Design Problem No. 1 Design Problem No. 2 Design Problem No. 3 Questions and Problems APPENDICES HP 64000 Motorola MC68000 and Support Chips-Data Sheets Intel 8085, 8086, and Support Chips-Data Sheets MC68000 Instruction Execution Times 8086 Instruction Set Reference Data Glossary Bibliography