Abstract: Design of Integrated Circuits for Optical Communications deals with the design of high-speed integrated circuits for optical communication systems. Written for both students and practicing engineers, the book systematically takes the reader from basic concepts to advanced topics, establishing both rigor and intuition. The text emphasizes analysis and design in modern VLSI technologies, particularly CMOS, and presents numerous broadband circuit techniques. Leading researcher Behzad Razavi is also the author of Design of Analog CMOS Integrated Circuits. Table of contents 1 Introduction to Optical Communications 2 Basic Concepts 3 Optical Devices 4 Transimpedance Amplifiers 5 Limiting Amplifiers and Output Buffers 6 Oscillator Fundamentals 7 LC Oscillators 8 Phase-Locked Loops 9 Clock and Data Recovery 10 Multiplexers and Laser Drivers

Abstract: A performance analysis of 1-bit full-adder cell is presented. The adder cell is anatomized into smaller modules. The modules are studied and evaluated extensively. Several designs of each of them are developed, prototyped, simulated and analyzed. Twenty different 1-bit full-adder cells are constructed (most of them are novel circuits) by connecting combinations of different designs of these modules. Each of these cells exhibits different power consumption, speed, area, and driving capability figures. Two realistic circuit structures that include adder cells are used for simulation. A library of full-adder cells is developed and presented to the circuit designers to pick the full-adder cell that satisfies their specific applications.

Abstract: Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.

Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Abstract: A three-dimensional, multi-chip package with chip selection pads formed at the chip-level and a manufacturing method thereof are provided. The three-dimensional, multi-chip package is formed by stacking a number (N) of semiconductor integrated circuit chips. Each chip comprises an integrated circuit die, a chip selection terminal, (N−1) chip selection pads, an insulation layer, (N−1) metal wirings, upper connection terminals, lower connection terminals, and trench wirings. The chip selection terminal of each chip is separated from the chip selection of the other chips by the chip selection pads formed at the chip-level.

Abstract: This paper reviews different techniques used in the litera ture to analyze distortion in analog integrated circuits. It concentrates on analytical techniques rather than on numerical techniques. Techniques such as Volterra series, harmonic injection method, and modeling of circuit non-linearities, are discussed with emphasis on the last tw o techniques. The theory behind each technique is e xplained, and they are compared together.

Abstract: A pattern-dependent model is used to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process. The process includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process, the lithography or etch process using a mask produced from the design. The lithography or etch process and the fabrication process interact to cause the predicted characteristics to differ from the design. The mask is adjusted in response to characteristics predicted by the model, to reduce the effect of the interacting of the lithography or etch process and the fabrication process. A location on an integrated circuit is predicted for which a lithography tool would not produce a satisfactory feature dimension without a degree of adjustment of the tool during fabrication to accommodate a focus limitation of the tool, and the design of at least one mask derived from the design is adjusted to enable the lithography tool to produce a satisfactory feature dimension at the locations. A virtual adjustment is effected of a distance of a lithographic tool from a location in a region of a wafer, the virtual adjustment being effected by using a mask having a mask layout that has been generated based on a pattern-dependent model prediction that the location in the region of the wafer would not otherwise have a satisfactory feature dimension due to a focus limitation of the lithographic tool. A pattern-dependent model is used to predict topography variations that will occur in an integrated circuit as a result of processing up to a predetermined lithographic process step, and designs of masks used in the lithographic process step are adjusted to accommodate the topography variations.

Abstract: A semiconductor module having a first integrated circuit die having a planar surface. The first integrated circuit die has a first conductive pad disposed substantially on the planar surface and a redistributed conductive pad electrically connected to the first conductive pad. The redistributed conductive pad is disposed near a periphery of the planar surface. The semiconductor module has a second integrated circuit die stacked adjacent to the planar surface and offset from the periphery, such that a second conductive pad on the second integrated circuit die can be electrically connected to the redistributed conductive pad.

Abstract: A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (“FPGA”) die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.

Abstract: A novel parasitic extraction system includes an interconnect primitive library that has a parameterized inductance function for at least one conducting layer of the integrated circuit. A parasitic extractor analyzes structures within a selected distance of a selected conductor within the integrated circuit and determines parasitic inductance values for the selected conductor using the parameterized inductance function of the interconnect primitive library. Using this parasitic extraction system, parasitic impedances, including inductance, may be extracted for an integrated circuit layout, thus allowing more accurate modeling and timing analysis of the integrated circuit layout to be obtained.

Abstract: An integrated circuit/optoelectronic packaging system ( 100 ) which comprises OE and IC components packaged to provide electrical input/output, thermal management, an optical window, and precise passive or mechanical alignment to external optical receivers or transmitters. A transparent insulating substrate having electrical circuitry in a thin silicon layer formed on its top side is positioned between the optical fiber and the optoelectronic device such that an optical path is described between the optoelectronic device and the optical fiber core through the transparent insulating substrate. The optoelectronic devices are mounted on the transparent insulating substrate in a precise positional relationship to guide holes in the substrate. The optical fibers are fixed in an optical fiber connector and are held in a precise positional relationship to guide holes in the connector. Alignment is accomplished with complementary guide pins that pass through guide holes in the fiber optic connector and in the transparent substrate.

Abstract: A method for fabricating semiconductor components and interconnects includes the steps of providing a substrate, such as a semiconductor die, forming external contacts on opposing sides of the substrate by laser drilling vias through the substrate, and forming conductive members in the vias. The conductive members include enlarged terminal portions that are covered with a non-oxidizing metal. The method can be used to fabricate stackable semiconductor packages having integrated circuits in electrical communication with the external contacts. The method can also be used to fabricate interconnects for electrically engaging packages, dice and wafers for testing or for constructing electronic assemblies.

Abstract: We introduce a new scheme for building three-dimensional (3D) integrated circuits (ICs) based on the layer transfer of completed devices. We demonstrate for the first time that the processes required for stacking active device layers preserve the intrinsic electrical characteristics of state-of-the-art short-channel MOSFETs and ring oscillator circuits, which is critical to the success of high performance 3D ICs.

Abstract: A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.

Abstract: A non-optical isolator having a driver circuit for providing an input signal to one or more first passive components which are coupled across a galvanic isolation barrier to one or more corresponding second passive components, and an output circuit that converts the signal from the second passive components to an output signal corresponding to the input signal. The entire structure may be formed monolithically as an integrated circuit on one or two die substrates, for low cost, small size, and low power consumption. The passive components may be coils (140, 142) or capacitor plates (130, 132, 134, 136), for example. When the first and second passive components are capacitor plates, a Faraday shield (51) may be provided between them, with the first and second passive components being referenced to separate grounds and the Faraday shield (51) referenced to the same ground as the second passive components.

Abstract: A method and apparatus are provided for depositing a filler material in a physical layout for an integrated circuit. The filler material is deposited on a layer by layer basis in the physical layout so that a channel length of the filler material has an orientation that differs between immediately adjacent layers. In addition, the filler materials in each of the layers are grouped into a first group and a second group wherein the filler material associated with the first group is coupled to a first portion of a power grid in the integrated circuit and the filler material associated with the second group is coupled to a second portion of the power grid in the integrated circuit. The tiller materials associated with each group are interconnected using one or more vias so that the filler material is capable of expanding the power grid of the integrated circuit to assist in the distribution of power throughout the various layers of the integrated circuit.

Abstract: An electrostatic discharge (ESD) protection circuit (302) in a semiconductor integrated circuit (IC) (100) having protected circuitry. In one embodiment, the ESD protection circuit (302) includes a pad (104), adapted for connection to a protected circuit node of the IC, and an ESD protection device (306), which is coupled between the pad and ground (112). A diode turn-on device (308) is coupled in a forward conduction direction from the pad to a first gate (336) of the ESD protection device. In a second embodiment, the ESD protection circuit (2002) is an SCR having an anode (322) coupled to a first voltage supply line, and a cathode coupled to ground. A parasitic capacitance (2004) is coupled between each the voltage supply line and the grounded cathode.

Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and metallic lines deposited on opposing surfaces of the first and second wafers at designated locations with an interlevel dielectric (ILD) recess surrounding the metallic lines to facilitate direct metal bonding between the first and second wafers and establish electrical connections between active IC devices on the first and second wafers.

Abstract: A rectifier circuit converts an alternating current into a direct-current voltage and outputs it as a power supply voltage. A ferroelectric holding circuit has a volatile holding circuit and a plurality of ferroelectric capacitors. Data held in the ferroelectric holding circuit has a read margin greater than that of data held in ferroelectric memory cells in a memory array. The ferroelectric holding circuit thus operates with reliability even if power that the semiconductor integrated circuit receives is low. Consequently, since the ferroelectric holding circuit is formed on the semiconductor integrated circuit to be implemented on an RFID transponder or a non-contact IC card, the communication range between the RFID transponder or non-contact IC card and a reader/writer can be extended.

Abstract: A printing cartridge (1001) includes a housing (1007). An integrated circuit device (1033) is positioned on the housing (1007). The integrated circuit device (1033) has memory circuitry that carries data relating to at least one of: a serial number of the cartridge, a media and a media colorant.

Abstract: An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. Plugs that extend from one surface of the wafer into the wafer are used to provide vertical connections and to bond the wafers together. A stacked integrated circuit is constructed by bonding the front side of a new wafer to a wafer in the stack and then thinning the backside of the new wafer to a thickness that leaves a portion of the plugs extending above the surface of the backside of the thinned wafer. The elevated plug ends can then be used to bond another wafer by bonding to pads on the front side of that wafer. The mating bonding pads can include depressed regions that mate to the elevated plug ends.

Abstract: One embodiment of the present invention provides a system that applies resolution enhancement techniques (RETs) selectively to a layout of an integrated circuit. Upon receiving the layout of the integrated circuit, the system identifies a plurality of critical regions within the layout based on an analysis of one or more of, timing, dynamic power, and off-state leakage current. The system then performs a first set of aggressive RET operations on the plurality of critical regions. The system also performs a second set of less aggressive RET operations on other non-critical regions of the layout.

Abstract: We describe a new procedure of design qualification to ensure manufacturability of deep sub-wavelength circuits. The procedure is based on optical simulation of the layout, integrated with device simulation of the layout, integrated with device simulation to meet predefined conditions set forth by the layout control lines called tolerance contours, a new concept proposed in this work, are first defined for active devices based on the geometry-dependent, target MOSFET parameters, such as ION and IOFF and for interconnecting lines, based on the resolution of the etch process, misalignment and overlap or enclosure of metal and contact layers. Drawn geometries, OPC features, or exposure conditions are then adjusted such that the simulated silicon images would fall within the tolerance contours. The concept is demonstrated on SRAM cell shrink from 120 to 100 nm technology nodes.© (2002) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Abstract: An integrated circuit design method and an integrated circuit design apparatus, for increasing an efficiency of parallel processing of LSI design layout data while retaining a hierarchical structure by use of a computer capable of processing the data in parallel, take a first construction of making an internal cell composed of divided cells obtained by dividing a design cell specified by design cell data among pieces of integrated circuit design layout data on the basis of a cell division judging criterion, and of non-divided design cells other than the divided cells, then creating a plurality of unit groups of which data quantities are substantially equal to each other by combining the internal cells, and executing hierarchical parallel processing of the data contained in the internal cell per unit group, and take a second construction of restoring a non-overlapped array data region left by excluding a data region having overlapped data from an array data region containing array data among pieces of integrated circuit design layout data, with a combination of a plurality of or a single piece of array cell or unit cell.

Abstract: Methods and apparatuses for designing an integrated circuit. In one example of a method, a hardware description language (HDL) code is compiled to produce a technology independent RTL (register transfer level) netlist. A portion of an area of the IC is allocated to a specific portion of the technology independent RTL netlist. In a typical implementation of this method, the allocation restricts circuitry created from the specific portion to the portion of the IC.

Abstract: A method of forming an integrated circuit package with an upward-facing chip cavity such that the fabrication of the substrate and the packaging of silicon chip are combined. By forming a patterned dielectric layer to expose bonding pads on a silicon chip and subsequently connecting the bonding pad on the chip with trace lines on the substrate through electroplating, reliable connections between the chip and substrate are formed and no more bubbles are formed inside the dielectric layer.

Abstract: A method for modeling integrated circuit designs in a hierarchical design automation system which utilizes a block abstraction including therein set of all database objects (cells, nets, wires, vias, and blockages) that are necessary to achieve accurate placement, routing, extraction, simulation, and verification of the block's ancestors in the hierarchy.

Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and a metal bonding layer deposited on opposing surfaces of the first and second wafers at designated locations to establish electrical connections between active IC devices on the first and second wafers and to provide metal bonding between the adjacent first and second wafers, when the first wafer is pressed against the second wafer using a flexible bladder press to account for height differences of the metal bonding layer across the opposing surfaces of the first and second wafers.

Abstract: Electrical through-wafer interconnects (ETWI) which connect devices between both sides of a substrate are critical components for microelectromechanical systems (MEMS) and integrated circuits (IC), as they enable three-dimensional (3-D) structures and permit new packaging and integration geometries. Previously demonstrated ETWI are very difficult to integrate with standard semiconductor fabrication processes, not compatible with released sensors, do not permit extensive processing on both sides of the wafer, and are in general very application specific. This work describes the design, fabrication, and characterization of an ETWI technology for silicon substrates that can be broadly integrated with MEMS and IC processes. This interconnect is a passively isolated electrical through-wafer polysilicon plug, with a 20 /spl mu/m diameter, 10-14 /spl Omega/ resistance, and less than 1 pF capacitance. Plasma etching from both sides of the wafer is used to achieve a high-aspect ratio via (20:1 through 400 /spl mu/m). The process is compatible with standard lithography, standard wafer handling, subsequent high-temperature processing, and released sensors integration. N-type and p-type versions are demonstrated, and isolated ground planes are added to provide shielding against substrate noise. Electrical properties of these ETWI are measured and analytically modeled. These ETWI are appropriate for integration with devices with impedances much greater than the ETWI, such as piezoresistive and capacitive sensor arrays.