TL;DR: In this article, the authors present new speed records for 128-bit secure elliptic-curve Diffie-Hellman key-exchange software on three different microcontroller architectures, including the AVR ATmega 8-bit, MSP430X 16-bit and ARM Cortex-M0 32-bit microcontrollers.
Abstract: This paper presents new speed records for 128-bit secure elliptic-curve Diffie---Hellman key-exchange software on three different popular microcontroller architectures. We consider a 255-bit curve proposed by Bernstein known as Curve25519, which has also been adopted by the IETF. We optimize the X25519 key-exchange protocol proposed by Bernstein in 2006 for AVR ATmega 8-bit microcontrollers, MSP430X 16-bit microcontrollers, and for ARM Cortex-M0 32-bit microcontrollers. Our software for the AVR takes only 13,900,397 cycles for the computation of a Diffie---Hellman shared secret, and is the first to perform this computation in less than a second if clocked at 16 MHz for a security level of 128 bits. Our MSP430X software computes a shared secret in 5,301,792 cycles on MSP430X microcontrollers that have a 32-bit hardware multiplier and in 7,933,296 cycles on MSP430X microcontrollers that have a 16-bit multiplier. It thus outperforms previous constant-time ECDH software at the 128-bit security level on the MSP430X by more than a factor of 1.2 and 1.15, respectively. Our implementation on the Cortex-M0 runs in only 3,589,850 cycles and outperforms previous 128-bit secure ECDH software by a factor of 3.
TL;DR: In this paper, a device configuration program with adaptive programming source code instructions that characterize device configuration instructions and data is presented, and an interpreter converts the program into formatted device configuration instruction and data.
Abstract: An apparatus and method for in-system programming of programmable devices includes a device configuration program with adaptive programming source code instructions that characterize device configuration instructions and data. The adaptive source code instructions may include conditional branches, subroutines, variables, configurable arrays, integer operators, and Boolean operators. These features allow for more compact and efficient device configuration instructions and data. An interpreter converts the device configuration program into formatted device configuration instructions and data. The formatted device configuration instructions and data are preferably compatible with IEEE 1149.1 JTAG-BST specifications. The formatted device configuration instructions and data are used to program a programmable device in the manner specified by the adaptive programming source code instructions.
TL;DR: In this article, a structure and method for in-system programming of a programmable logic device is described, which can be cascaded in a "daisy chain" fashion.
Abstract: A structure and method for in-system programming of a programmable logic device are provided. The in-system programming structure provides one dedicated pin for in-system programming function, additional in-system programming pins are multiplexed with programmable input/output pins used in functional operations. When an enable signal is received at the dedicated pin, the multiplexed pins relinquish their roles as programmable input/output pin to become in-system programming pins. A state machine controls the programming steps. The in-system programming structure can be cascaded in a "daisy chain" fashion.
TL;DR: In this article, a programmable resistive memory (PRSM) is used to generate feedback as to when the device has been programmed and to remove the programming power when the feedback indicates that the device had been programmed.
Abstract: Programming of a programmable resistive memory device includes supplying programming power to the device; generating feedback as to when the device has been programmed; and removing the programming power when the feedback indicates that the device has been programmed.
TL;DR: In this paper, the authors present a method to implement in-system programming (ISP) and boundary-scan testing in an integrated circuit using the same pins to control both functions.
Abstract: A structure and a method to implement in-system programming (ISP) and boundary-scan testing in an integrated circuit using the same pins to control both functions. The SDI, SCLK, MODE and SDO connections required for in-system programming and the TDI, TCK, TMS and TDO connections required for boundary-scan testing are multiplexed such that they are provided from the same four pins. An in-system programming enable pin is used to control the multiplexing of these pins. In an alternative embodiment, both in-system programming and boundary-scan testing are performed using the same pins and the same state machine. The test logic architecture specified in IEEE Standard 1149.1-1990 is utilized. To implement the in-system programming instructions, the instruction register of Std. 1149.1-1990 is modified to include private instructions which perform the desired programming functions.