IMD3

Abstract: Dynamic performance of high-speed high-resolution digital-to-analog converters (DACs) is limited by distortion at the data switching instants. Inter-symbol interference (ISI), imperfect timing synchronization, and clock jitter are all culprits. A DAC output controlled by an oscillating waveform is proposed to mitigate the effects of switching distortion and clock jitter. This architecture has the additional benefit of mixing the DAC impulse response energy to a higher frequency, allowing a high-frequency image of the input to be used as the output. This has the potential for better noise performance and power and hardware savings relative to a conventional DAC+mixer architecture. A narrow-band sigma-delta (/spl Sigma//spl Delta/) DAC with eight unit elements is chosen to demonstrate the radio frequency digital-to-analog converter (RF DAC) concept in a 1.8-V 0.18-/spl mu/m CMOS technology. Measured single-tone SFDR is -75 dBc, SNR is 53 dB, and two-tone IMD3 is -70.8 dBc for a 17.5-MHz band centered at 942 MHz. SNR performance is shown to have the predicted dependence on the phase alignment of the data clock and oscillating pulse.

Abstract: To overcome the problem of fabrication complexity and to reducei the cost of microelectronic devices, a new concept of dual-material control gate with dual-oxide tunnel field-effect transistor is investigated. A stack gate approach is applied to reduce the width of tunneling barrier at source–channel junction. Use of dual oxides at source–channel interface provides improved capacitive coupling, which enhances the on-state current. The entire gate segment has been partitioned into three parts, namely tunnel gate $$(M_1)$$, control gate $$(M_2)$$ and auxiliary gate $$(M_3)$$ with different work functions such as $$\phi _{1}$$, $$\phi _{2}$$ and $$\phi _{3}$$. In this context, to keep dual-work functionality, the feasible combinations of these work functions are adopted. Technology computer- aided design (TCAD) simulations of these proposed combinations of work functions along with dual oxides provide better results for the combinations of $$(\phi _1=\phi _3<\phi _2)$$. In addition, comparison between these combinations on the basis of analog/RF performance is done in this work. This work shows improved analog/RF parameters such as $$g_\text {m}, C_\text {gs}, C_\text {gd}, f_\text {T}$$ and TFP, and linearity parameters including $$g_\text {m3}, \text {VIP3, IIP3}$$ and $$\text {IMD3}$$ for the proposed device DMDODG-TFET (dual-material dual-oxide double-gate TFET). The use of this proposed device structure reduces the ambipolar behavior and subthreshold swing $$(18.5\,\text {mV}/\text {deacde})$$, and enhances the on-current [$$3.6\times 10^{-5}\,(A/\upmu \text {m})$$] significantly, making it suitable for analog/RF and linearity applications.

Abstract: In this paper, we investigate for the first time effect of positive (donor) and negative (acceptor) interface trap charges on the performance of proposed heterogeneous gate dielectric (HD) electrically doped tunnel field-effect transistor (EDTFET) in terms of dc, analog/RF, and linearity distortion parameters, where the HD layer is considered as a gate dielectric to improve the ON-state current and device performance. For this, a comparative analysis has been performed between conventional and proposed EDTFET with identical dimensions in the presence of interface trap charges. ATLAS device simulation of both devices is performed for different performance metrics such as transfer characteristics, parasitic capacitances, device efficiency, output conductance ( $\text{g}_{ {ds}}$ ), cut-off frequency ( $\text{f}_{ {t}}$ ), and gain bandwidth product. However, linearity distortion parameters of the proposed device such as third-order transconductance coefficient ( $\text{g}_{ {m3}}$ ), VIP2, VIP3, IIP3, and IMD3 are also investigated. The device simulations show that HD-EDTFET is more immune in terms of performance variation than conventional EDTFET with different interface trap charges available at the Si/SiO2 interface. Thus, it can be utilized as a suitable candidate for low power analog/RF applications.

Abstract: In this article, two nanotube structures have been proposed: namely, core–shell dopingless nanotube tunnel field effect transistor (CS-DL-NT-TFET) and Si0.5Ge0.5 source CS-DL-NT-TFET. The application of charge-plasma (CP) technique in their designing offers a fabrication advantage, which is the elimination of doping. Performance analysis of the two nanotube structures has been carried out on the basis of RF and analog parameters such as their transconductance ( ${g}_{m}$ ), transfer characteristics ( ${I}_{D}$ – ${V}_{{\text {GS}}}$ ), output conductance ( ${g}_{{\text {ds}}}$ ), output characteristics ( ${I}_{D}$ – ${V}_{{\text {DS}}}$ ), cut-off frequency ( ${f}_{T}$ ), and gate capacitance ( ${C}_{{\text {gg}}}$ ). Furthermore, the two devices have also been investigated for linearity and reliability based on parameters such as higher-order transconductances ( ${g}_{{\textit {m3}}}$ and ${g}_{{\textit {m2}}}$ ), distortions [second-order harmonic distortion (HD2)], interception points [third-order input interception point (IIP3), second-order voltage interception point (VIP2), and third-order voltage interception point (VIP3)], and intermodulation distortion [third-order intermodulation distortion (IMD3)]. Based on the analysis of different parameters, the Si0.5Ge0.5 source CS-DL-NT-TFET was observed to have achieved an improved performance as compared to its Si-source counterpart due to a lower energy bandgap, higher mobility, and lower tunneling mass. The proposed device is optimized to maintain the uniformity of the induced CP within the source/drain regions. The optimized architecture enhances the device performance by attaining an average subthreshold slope of 31.38 mV/dec with a higher ON-current.