Iddq testing

Abstract: It is little more than 15-years since the idea of Iddq testing was first proposed. Many semiconductor companies now consider Iddq testing as an integral part of the overall testing for all IC's. This paper describes the present status of Iddq testing along with the essential items and necessary data related to Iddq testing. As part of the introduction, a historical background and discussion is given on why this test method has drawn attention. A section on physical defects with in-depth discussion and examples is used to illustrate why a test method outside the voltage environment is required. Data with additional information from case studies is used to explain the effectiveness of Iddq testing. In Section IV, design issues, design styles, Iddq test vector generation and simulation methods are discussed. The concern of whether Iddq testing will remain useful in deep submicron technologies is addressed (Section V). The use of Iddq testing for reliability screening is described (Section VI). The current measurement methods for Iddq testing are given (Section VII) followed by comments on the economics of Iddq testing (Section VIII). In Section IX pointers to some recent research are given and finally, concluding remarks are given in Section X.

Abstract: This paper studies some manufacturing test data collected for an experimental digital IC. Test results for a large variety of single-stuck fault based test sets are shown and compared with a number of test sets based on other fault models. The defects present in the chips studied are characterized based on the chip tester responses. The data presented shows that N-detect test sets are particularly effective for both timing and hard failures. In these test sets each single-stuck fault is detected by at least N different test patterns. We also present data on the use of IDDq tests and VLV (very low voltage) tests for detecting defects whose presence doesn't interfere with normal operation during manufacturing test, but which cause early life failure.

Abstract: Quiescent power supply current (I DDQ ) testing of CMOS integrated circuits is a technique for production quality and reliability improvement, design validation, and failure analysis. It has been used for many years by a few companies and is now receiving wider acceptance as an industry tool. This article begins with a brief history of CMOS ICs to provide perspective on the origin of I DDQ testing. Next, the use of I DDQ testing for IC quality improvement through increased defect and fault detection is described. Then implementation issues are considered, including test pattern generation software, hardware instrumentation, limit setting, IC design guidelines, and defect diagnosis. An extended reference list is provided to help the reader obtain more information on specific aspects.

Abstract: Current testing has been found to be useful for testing CMOS ICs because it can detect a large class of manufacturing defects. The concept of current testing is described; the classes of defects detectable by current testing and the conditions to detect a given defect are described; and a general test-vector generation algorithm for current testing is developed and applied to two examples. >