IC layout editor

Abstract: Feel lonely? What about reading books? Book is one of the greatest friends to accompany while in your lonely time. When you have no friends and activities somewhere and sometimes, reading book can be a great choice. This is not only for spending the time, it will increase the knowledge. Of course the b=benefits to take will relate to what kind of book that you are reading. And now, we will concern you to try reading combinatorial algorithms for integrated circuit layout as one of the reading material to finish quickly.

Abstract: Subtleties of advanced fabrication processes and nano-scale phenomena associated with integrated circuit miniaturization have exposed the insufficiencies of design rules. Such inadequacies have adverse impact on all parts of the integrated circuit creation flow where design rules are used. In addition, segregation of the various layout data modification steps required for deep sub-micrometer manufacturing are resulting in slack and inefficiencies. This invention describes methods to improve integrated circuit creation via the use of a unified model of fabrication processes and circuit elements that can complement or replace design rules. By capturing the interdependence among fabrication processes and circuit elements, the unified model enables efficient layout generation, resulting in better integrated circuits.

Abstract: A method and system for performing layout verification on an integrated circuit (IC) design using reusable subdesigns. Many custom designed integrated circuits are designed and fabricated using a number of computer implemented automatic design processes. Within these processes, a high level design language (e.g., HDL or VHDL) description of the integrated circuit can be translated by a computer system into a netlist of technology specific gates and interconnections there between. The cells of the netlist are then placed spatially in an integrated circuit layout and the connections between the cells are routed using computerized place and route processes. Circuit designers next run layout verification tests on the layout to verify that the geometry and connectivity data of the design meets specific design rules and matches logically with the schematic representation. The present invention provides a method of layout verification where unchanged subdesigns of a hierarchical IC design can be reused upon subsequent verification processes of the same IC design. They are reused for both design rule checking (DRC) and layout versus schematic (LVS) comparison. By reusing some of the subcell designs, subsequent verification processes of the present invention can be performed very efficiently. To account for faults attributed to subcell interfaces, the present invention advantageously determines subcell overlap areas within the layout and selectively flattens and verifies these areas in addition to any subcell designs that were not previously validated. Further, the invention determines updated connectivity information for new subcell designs.

Abstract: A new method of packing the rectangles (modules) is presented with applications to IC layout design. It is based on the bounded-sliceline grid (BSG) structure. The BSG dissects the plane into rooms associated with binary relations ``right-to''and ``above'' such that any two rooms are uniquely in either relation. A packing is obtained through an assignment of modules on the BSG, followed by physical realization BSG-PACK. A simulated annealing searches for a good packing of all packings by changing the assignments. Experiments showed that hundreds of rectangles are easily packed in a small rectangle area (chip) with a quite good quality in area efficiency. A wide adaptability is demonstrated specific to IC layout design. Remarkable examples are: the chip is not necessarily rectangle, L-shaped modules and modules which are allowed to partially overlap each other can be handled.