High-Speed Serial Interface

Abstract: A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

Abstract: A vehicle computer system has a housing sized to be mounted in a vehicle dashboard or other appropriate location. The housing includes a base unit and a faceplate. A first logic unit is mounted to the base unit to form a support module. The support module has two interfacing slots and can support connections to multiple peripheral devices. The support module facilitates high speed data exchange between the peripheral devices for streaming continuous audio or video data. The support module has a fast data memory to temporarily hold data being communicated between the peripheral devices. The support module also has a memory access circuit associated with each of the peripheral devices which designates at least one storage area within the fast data memory to hold data received from, or to be sent to, the associated peripheral device. The vehicle computer has a computer module which can be connected to or removed from one interfacing slot of the support module. A multi-bit bus (e.g., PCI bus) interfaces the computer module and the support module. The vehicle computer system also has a logic unit mounted to the faceplate to form a faceplate module. This module is detachably connected to the other interfacing slot of the support module. When the faceplate module is attached, a high speed serial interface electronically couples the support module to the faceplate module. The high speed serial interface enables the logic units on the support and faceplate modules to exchange a high speed, synchronized, serial bit stream. This data stream is organized into multiple frames, with each frame having multiple data bits and at least one valid bit to indicate whether the data bits are valid.

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract: A high speed, two-way serial interface with a scrambler and de-scrambler may be tested by sending a single word repeatedly through the scrambler to create a pseudo-random sequence The pseudo-random sequence is then passed through the transmitter and looped back through the receiver of the serial interface The pseudo-random sequence is then descrambled and compared to the input word Since the input sequence is only a single word rather than a series of words, the comparison is very simple and capable of being performed within the serial interface itself without the need for external test equipment