Hexadecimal time

Abstract: The invention relates to a gateway communication data time synchronization method based on an FPGA + ARM architecture. The method comprises the following steps that 1, a gateway communication module receives an IRIG-B code and inputs the IRIG-B code into an FPGA; 2, the FPGA analyzes the time information of a BCD system according to the coding format of the IRIG-B code; 3, the day information is converted into month and day information; 4, the FPGA converts the time information of the BCD system into hexadecimal information, and performs CRC coding on all the time information; 5, the FPGA writes hexadecimal time information and a CRC check value into the FPGA and ARM read-write operation shared RAM area according to the data format of the FPGA and ARM shared RAM area; 6, the FPGA starts timing for 410ms only after successfully analyzing the complete time information ta; 7, the ARM generates interruption after receiving the second pulse PPSa; 8, the ARM judges whether the arrival time of the second pulse PPSa is within the deviation range of 997 ms to 1,000 ms of the counter or not. The method is high in precision, is low in power consumption, is stable in performance, is fast in transmission and can achieve the high anti-interference capability.