TL;DR: In this article, double edge-triggered D flip-flops (DETDFFs) are proposed to respond to both edges of the clock pulse, which has advantages in terms of power dissipation and speed.
Abstract: Two circuits are proposed for double edge-triggered D flip-flops (DETDFFs). A DETDFF responds to both edges of the clock pulse. As compared with positive or negative edge-triggered flip-flops, a DETDFF has advantages in terms of power dissipation and speed. Delay figures for these circuits are measured by simulation. It is shown that these circuits are faster and have lower transistor counts than previously reported circuits. It is shown that these flip-flops can be used at 320-400-MHz clock frequency in a 2- mu m technology. >
TL;DR: SiGe is just on an upswing and outstanding performance was even demonstrated, e.g. high frequencies above 100 GHz, low noise below 0.5 dB at 2 GHz, high transconductances around 400 mS/mm as discussed by the authors.
Abstract: SiGe is just on an upswing. Attractive potentials can be foreseen and outstanding performance was even demonstrated, e.g. high frequencies above 100 GHz, low noise below 0.5 dB at 2 GHz, high transconductances around 400 mS/mm. A further driving force for the growing engagement with SiGe is its basic compatibility to standard Si-technology. Though most of the results stem from discrete devices SiGe is already going to be produced. The first devices will be SiGe-heterobipolar transistors (HBT). Targeted applications are converters or mobile communication systems. The status of our devices is reviewed here. In long term the SiGe hetero fieldeffect transistor (HFET) will become another candidate creating a new advanced generation in mainstream CMOS, s.c. SiGe Hetero CMOS (HCMOS). Our status of SiGe HFETs and its potential for HCMOS is presented also.
TL;DR: In this article, a wireless communication block with the antenna integration was designed and integrated on advanced sub 120nm HCMOS high resistivity silicon on insulator (HR SOI) (p > 1 kOhms).
Abstract: Today, SiGe HBT and MOSFET cut-off frequencies are higher than 230 GHz (Chevalier et al., 2004) and this increase allows new millimeter wave (MMW) applications on silicon such as 60 GHz WLAN and 77 GHz automotive radar. This study focuses on a wireless communication block with the antenna integration. Functions such as amplifier and filter have been used to perform this block. This is a demonstration of individual component integration and co-integration with antenna/LNA matching. Antenna achieved on advanced sub 120nm HCMOS high resistivity silicon on insulator (HR SOI) (p >1 kOhms.cm) has been designed and integrated. A low noise amplifier (LNA) and a filter have been retained for this first chain. Antenna and block characterizations are led on a dedicated on-wafer test bench. Antenna performances in term of gain and radiation pattern are given. A communication link has been then established between a single antenna (-2 dB gain) and the full communication block with a -19 dB transmission gain at 40 GHz.
TL;DR: The design and implementation of the RISC (reduced-instruction-set computer) 88000 system in high-speed, complementary metal-oxide semiconductor (HCMOS) technology is described and the various features and components are discussed.
Abstract: The design and implementation of the RISC (reduced-instruction-set computer) 88000 system in high-speed, complementary metal-oxide semiconductor (HCMOS) technology is described. The total system consists of the 88100 processor and two 88200 cache memory management units (CMMUs). The various features and components of the 88000 are discussed. >
TL;DR: In this article, a gate array is provided in which active areas within the substrate are arranged in alternating columns of opposite conductivity type and symmetrical about the center lines through each column so that CMOS devices can be advantageously formed by allocating only small increments of active area to metal routing.
Abstract: A gate array is provided in which active areas within the substrate are arranged in alternating columns of opposite conductivity type and symmetrical about the center lines through each column so that CMOS devices can be advantageously formed by allocating only small increments of active area to metal routing. The substrate and well taps are also symmetrical about the column center line. The active area symmetry allows p-channel and n-channel transistors to be combined where the p-channel transistor is on either the right or left, thus increasing the flexibility in placing the elements within the integrated circuit chip.