Global Descriptor Table

Abstract: One or more virtual machines (VM's) run via a virtual machine monitor (VMM) on a hardware platform that has a segmented memory architecture. Each VM has at least one VM descriptor table that has, as entries, VM segment descriptors. At least one VMM descriptor table is established, including at least one shadow descriptor table that stores shadow descriptors for certain of the VM segment descriptors, which are then shadowed descriptors. The VMM compares the shadow descriptors with their respective corresponding shadowed VM descriptors, detects any lack of correspondence between the shadow descriptor table and the corresponding VM descriptor table, and updates and thereby synchronizes each shadow descriptor with its respective shadowed VM descriptor no later than, and preferably only upon the first use of, the respective descriptor by the VM. Whenever the VMM detects any attempt by the VM to load an usynchronized shadowed descriptor, the VMM verifies that the VM is allowed to load it, and then establishes synchronization for the pair of descriptors. One detection mechanism is the tracing of entire memory pages in which VM descriptors are stored; another involves sensing and setting the state of a segment present bit for individual descriptors. The invention improves virtualization performance by reducing the number of descriptors that need to be kept coherent. The VMM also has a flexible mechanism to invalidate descriptors, for example, when the VM unmaps or remaps the memory page it is located in, or when the VM sets a new segment descriptor table.

Abstract: A microprocessor contains an address generation unit, including a segment block, for loading descriptor data and a segment selector in a segment register. Two descriptor loads from a global descriptor table (GDT) and a local descriptor table (LDT) are executed. A 64 bit global descriptor from the GDT is loaded into a temporary register, and a 64 bit local descriptor from the LDT is also loaded into a separate temporary register. If a table indicator bit in the segment selector indicates use of the GDT, then the descriptor data from the GDT is selected. Alternatively, if the table indicator bit in the segment selector indicates the use of the LDT, then the descriptor data from the LDT is selected. The segment block splits the 64 bit descriptor data selected into two 32 bit quantities. The two 32 bit data quantities are input to a test programmable logic array (PLA). The test PLA checks for permission violations, or faults, and detects the need for special handling of the register segment load operation. If a fault violation occurs, the segment block signals a fault exception. If no fault is detected, then the segment block loads the two 32 bit descriptor data segments, along with the selector, into the appropriate segment register. If special handling is required, a conditional indirect branch is utilized to reach the handler.

Abstract: A computer system emulates segment bounds checking with a paging system. Pages entirely within a segment are designated as `clear pages`, while the first and last pages containing segment bounds may be partially-valid pages. The computer system has a memory with a segment descriptor table and an active segment descriptor cache. The active segment descriptor cache holds a copy of the segment descriptors for the active segments in a central processing unit (CPU). The active segment descriptor cache also hold the first and last clear page numbers and the first and last linear address offsets for the active segment. A software segment load routine copies portions of the segment descriptor from the segment descriptor table to the active segment descriptor cache when a user program loads a new segment. Only the segment base address is copied to the CPU die; the segment limit and selector need not be stored on the CPU die. The CPU has a translation-lookaside buffer (TLB) that includes bounds fields and a comparator for signaling when an offset portion of a linear address is outside the bound on a page. A TLB miss routine compares the linear address to the first and last clear pages in the active segment descriptor cache and loads a fully-valid page if the linear address is between the first and last clear pages, but loads the bounds field with the page offset of the segment bound if the linear address is to a partial page at the bounds of the segment.

Abstract: An arrangement for dynamically translating virtual address into absolute or physical addresses of items of data. Each virtual address includes a segment table number, a segment table entry, and a segment page number. Segment descriptors are stored in a central memory. The address of a particular segment descriptor may be calculated from the segment table number and the segment table entry. From the segment descriptor, a unique identification termed a logic page number may be calculated. The logic page number permits pseudo-associative access to a table containing a number of entries proportional to the number of physical pages of the main memory, allowing the physical address to be determined.