Topic
Gate equivalent
About: Gate equivalent is a research topic. Over the lifetime, 2016 publications have been published within this topic receiving 34078 citations.
Papers published on a yearly basis
1 / 2
Papers
TL;DR: This work demonstrates an organic circuit with very low power consumption that uses a self-assembled monolayer gate dielectric and two different air-stable molecular semiconductors (pentacene and hexadecafluorocopperphthalocyanine, F16CuPc) to implement transistors, circuits, displays and sensors on arbitrary substrates.
Abstract: Organic transistors and circuits show great promise for the realization of futuristic roll-up displays, adaptive sensors for humanoid robots and ubiquitous radio-frequency identification tags. But today's organic circuits require operating voltages of 15 to 30 volts (10 to 20 batteries' worth), and they draw enough power to drain those batteries in a day. To overcome this major hurdle, Hagen Klauk et al. have developed a method of fabricating organic circuits that run on a single 1.5-volt battery for several years. The key to the method is the use of a layer of an insulating organic material just one molecule thick; although the layer is very thin, it leaks only a small amount of current, while it provides for a large capacitance. Two different types of organic semiconductors are used to fabricate transistors, logic gates and ring oscillators. A report of the development of organic electronic circuits, which require only a single 1.5V battery and last for several years. The main ingredient is the use of a single layer of an insulating organic material. Although the layer is very thin, it leaks only small amount of current, while providing for a large capacitance. The prospect of using low-temperature processable organic semiconductors to implement transistors, circuits, displays and sensors on arbitrary substrates, such as glass or plastics, offers enormous potential for a wide range of electronic products1. Of particular interest are portable devices that can be powered by small batteries or by near-field radio-frequency coupling. The main problem with existing approaches is the large power consumption of conventional organic circuits, which makes battery-powered applications problematic, if not impossible. Here we demonstrate an organic circuit with very low power consumption that uses a self-assembled monolayer gate dielectric and two different air-stable molecular semiconductors (pentacene and hexadecafluorocopperphthalocyanine, F16CuPc). The monolayer dielectric is grown on patterned metal gates at room temperature and is optimized to provide a large gate capacitance and low gate leakage currents. By combining low-voltage p-channel and n-channel organic thin-film transistors in a complementary circuit design, the static currents are reduced to below 100 pA per logic gate. We have fabricated complementary inverters, NAND gates, and ring oscillators that operate with supply voltages between 1.5 and 3 V and have a static power consumption of less than 1 nW per logic gate. These organic circuits are thus well suited for battery-powered systems such as portable display devices2 and large-surface sensor networks3 as well as for radio-frequency identification tags with extended operating range4.
1,438 citations
TL;DR: This work demonstrates complete characterization of a two-qubit entangling process--a linear optics controlled-NOT gate operating with coincident detection--by quantum process tomography by using a maximum-likelihood estimation to convert the experimental data into a physical process matrix.
Abstract: We demonstrate complete characterization of a two-qubit entangling process-a linear optics controlled-NOT gate operating with coincident detection-by quantum process tomography. We use a maximum-likelihood estimation to convert the experimental data into a physical process matrix. The process matrix allows an accurate prediction of the operation of the gate for arbitrary input states and a calculation of gate performance measures such as the average gate fidelity, average purity, and entangling capability of our gate, which are 0.90, 0.83, and 0.73, respectively.
611 citations
TL;DR: Fully depleted tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated in this article, where the transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages.
Abstract: Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 - 2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.
539 citations
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.
525 citations
17 Jun 2008
TL;DR: In this article, two key process features that are used to make 45 nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper.
Abstract: Two key process features that are used to make 45 nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper. The first feature is the integration of stress-enhancement techniques with the dual metal-gate + high-k transistors. The second feature is the extension of 193 nm dry lithography to the 45 nm technology node pitches. Use of these features has enabled industry-leading transistor performance and the first high volume 45 nm high-k + metal gate technology.
291 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2025 | 1 |
| 2024 | 2 |
| 2023 | 9 |
| 2022 | 9 |
| 2021 | 4 |
| 2020 | 2 |