Topic
Futurebus
About: Futurebus is a research topic. Over the lifetime, 81 publications have been published within this topic receiving 1494 citations. The topic is also known as: IEEE 896.
Papers published on a yearly basis
Papers
1 May 1986
TL;DR: This paper defines a class of compatible consistency protocols supported by the current IEEE Futurebus design, referred to as the MOESI class of protocols, which has the property that any system component can select (dynamically) any action permitted by any protocol in the class, and be assured that consistency is maintained throughout the system.
Abstract: Standardization of a high performance blackplane bus, so that it can accommodate boards developed by different vendors, implies the need for a standardized cache consistency protocol. In this paper we define a class of compatible consistency protocols supported by the current IEEE Futurebus design. We refer to this class as the MOESI class of protocols; the term “MOESI” is derived from the names of the states. This class of protocols has the property that any system component can select (dynamically) any action permitted by any protocol in the class, and be assured that consistency is maintained throughout the system. Included in this class are actions suitable for copyback caches, write through caches and non-caching processors. We show that the Berkeley protocol and the Dragon protocol fall within this class, and can be extended to be compatible with other members of the class. The Illinois, Firefly and Write-Once protocols can be adapted to be compatible with this class; the facilities of he Futurebus currently do not support those protocols without adaptation. We discuss very briefly performance choices among protocols, and also other issues relating to a standard bus consistency protocol.
314 citations
26 Apr 1993
TL;DR: A hardware description language is used to construct a formal model of the cache coherence protocol described in the IEEE Futurebus+ standard, and temporal logic model checking techniques are applied to find errors in the standard.
Abstract: We used a hardware description language to construct a formal model of the cache coherence protocol described in the IEEE Futurebus+ standard. By applying temporal logic model checking techniques, we found errors in the standard. The result of our project is a concise, comprehensible and unambiguous model of the protocol that should be useful both to the Futurebus+ Working Group members, who are responsible for the protocol, and to actual designers of Futurebus+ boards.
165 citations
IBM1
TL;DR: The proposed IEEE 896 backplane bus for multimicroprocessor systems synchronizes processes to arbitrate between devices seeking control of the bus simultaneously.
Abstract: The proposed IEEE 896 backplane bus for multimicroprocessor systems synchronizes processes to arbitrate between devices seeking control of the bus simultaneously.
68 citations
TL;DR: In this article, a bidirectional optical backplane bus for a high performance system containing nine multi-chip module (MCM) boards, operating at 632.8 and 1300 nm, is presented.
Abstract: We report for the first time a bidirectional optical backplane bus for a high performance system containing nine multi-chip module (MCM) boards, operating at 632.8 and 1300 nm. The backplane bus reported here employs arrays of multiplexed polymer-based waveguide holograms in conjunction with a waveguiding plate, within which 16 substrate guided waves for 72 (8/spl times/9) cascaded fanouts, are generated. Data transfer of 1.2 Gbt/s at 1.3-/spl mu/m wavelength is demonstrated for a single bus line with 72 cascaded fanouts. Packaging-related issues such as transceiver size and misalignment are embarked upon to provide a reliable system with a wide bandwidth coverage. Theoretical treatment to minimize intensity fluctuations among the nine modules in both directions is further presented and an optimum design rule is provided. The backplane bus demonstrated, is for general-purpose and therefore compatible with such IEEE standardized buses as VMEbus, Futurebus and FASTBUS, and can function as a backplane bus in existing computing environments. >
67 citations
23 Oct 1995
TL;DR: The first bidirectional optical backplane bus for a high performance multiprocessor system operating at wavelengths of 632.8 nm and 1300 nm is reported, and theoretical treatment to minimize fluctuations among the received power at each processor/memory board is presented.
Abstract: We report the first bidirectional optical backplane bus for a high performance multiprocessor system operating at wavelengths of 632.8 nm and 1300 nm. The optical backplane employs an array of multiplexed holograms, in conjunction with a waveguiding plate within which cascaded fanouts are generated. Data transfer rate of 1.2 Gbit/sec at 1300 nm is demonstrated with a single bus line for a system composed of nine processor/memory boards. To provide a reliable system, packaging-related issues, such as the detector size and misalignment effects are addressed. Theoretical treatment to minimize fluctuations among the received power at each processor/memory board is further presented and an optimum design rule is provided. The backplane demonstrated here is for general-purpose. It can support standard multiprocessor buses such as Futurebus+, Multibus II, etc. It also can function as a backplane bus in existing computing systems and significantly reduce the bottlenecks that accompany electrical interconnects.
40 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2004 | 1 |
| 2002 | 1 |
| 2001 | 1 |
| 2000 | 3 |
| 1999 | 3 |
| 1998 | 1 |