TL;DR: In this article, the authors propose a virtual first-in-first-out stack structure with a data stack and a split control stack, which is intended for use in a pipelined high performance storage unit that can pipeline up to R input requests without having received an acknowledge that a request has been honored.
Abstract: A high performance pipelined virtual first-in first-out stack structure has a data stack portion and a split control stack portion. The stack structure is intended for use in a pipelined high performance storage unit that can pipeline up to R input requests without having received an acknowledge that a request has been honored. The data stack incorporates R+1 data stack registers to provide over-write protection to ensure that at least R data stack registers are protected from over-write. The split control stack utilizes even address and odd address stack registers. Memory bank request signals are stored sequentially and alternately between the even address and odd address stack registers. An even address read pointer and an odd address read pointer under control of a read pointer control circuit alternates the selection for read out sequentially between the even address and odd address stack registers that decoding of the memory bank request signals for the next reference can be interleaved with completion of the decoding and prioritization of the current stack register. Advancement of stack register addresses at which writing will take place is under control of a request signal. Control of the read pointers for the data stack and split control stack are responsive to bank acknowledge signals received by the read pointer control circuits.
TL;DR: In this article, the ShadowKEY value on a function's call stack frame is replaced by a copy of the Shadowkey, caller EBP, and return pointer on a duplicate stack.
Abstract: Improved buffer overflow protection for a computer function call stack is provided by placing a predetermined ShadowKEY value on a function's call stack frame and copying the ShadowKEY, a caller EBP, and a return pointer are pushed onto a duplicate stack. The prologue of the function may be modified for this purpose. The function epilogue is modified to compare the current values of the ShadowKEY, caller EBP, and the return pointer on the function stack to the copies stored on the duplicate stack. If they are not identical, an overflow is detected. The preserved copies of these values may be copied back to the function stack frame thereby enabling execution of the process to continue. A function prologue and epilogue may be modified during compilation of the program.
TL;DR: An assembly-language type system capable of ensuring memory safety in the presence of both heap and stack allocation is described, and Micro-CLI, a simple imperative language that captures the essence of stack allocation in the common language infrastructure is defined.
Abstract: This paper describes an assembly-language type system capable of ensuring memory safety in the presence of both heap and stack allocation The type system uses linear logic and a set of domain-specific predicates to specify invariants about the shape of the store Part of the model for our logic is a tree of "stack tags" that tracks the evolution of the stack over time To demonstrate the expressiveness of the type system, we define Micro-CLI, a simple imperative language that captures the essence of stack allocation in the common language infrastructure We show how to compile well-typed Micro-CLI into well-typed assembly
TL;DR: In this chapter the basics of Cortex-M3 basics have been discussed in detail and the readers get an idea about the basic concept of Stack Memory, Vector Table, the PUSH and POP operations as well as Special Registers and its uses.
Abstract: In this chapter the basics of Cortex-M3 basics have been discussed in detail. It explains the registers of Cortex-M3 processor, their general purpose and the difference between low registers and high registers. The readers also get an idea about the basic concept of Stack Memory, Vector Table, the PUSH and POP operations as well as Special Registers and its uses. The Cortex-M3 processor supports two modes and two privilege levels as well as a number of exceptions. This includes a fixed number of system exceptions and a number of interrupts, which is commonly called IRQ.
TL;DR: In this paper, a method of debugging a function upon function exit includes pausing program execution at the time of initializing the function, wherein the function initialization includes saving a set of registers on the stack, recording the value of the stack pointer, configuring a watchpoint register based on the recorded value, and executing the function.
Abstract: A method of debugging a function upon function exit includes pausing program execution at the time of initializing the function, wherein the function initialization includes saving a set of registers on the stack, recording the value of the stack pointer, configuring a watchpoint register based on the recorded value, wherein the watchpoint register is configured to trap memory references of the function based on the recorded value of the stack pointer, and executing the function. Program execution will pause when it is exiting the function because of stack references made by the function epilogue to restore registers saved on the stack and the configured watchpoint registers.