FO4

Abstract: The ability to produce a high-performance monolithic CMOS photoreceiver, including the photodetector, could enable greater use of optics in short-distance communication systems. Such a receiver requires the ability to simultaneously produce a photodetector compatible with a high-volume high-yield CMOS process, as well as the entire receiver circuit. The quest for this element has yet to produce a clear winner, and has proven quite challenging. We review some of the work in this field with the goal of informing the reader as to the origin of the challenges and the implementation tradeoffs. Finally, we report experimental results from a monolithic CMOS photoreceiver realized in a 0.35-/spl mu/m production CMOS process, including a CMOS photodiode. Operating at 1 Gb/s, the receiver requires an average input power of -6.3 dBm at 850 nm to obtain a measured bit error rate of 1/spl times/10/sup -9/, and dissipates 1.5 mW at 2.2 V, increasing to 6 mW at 3.3 V.

Abstract: A low-voltage, low-power CMOS delay element is proposed. With a unit CMOS inverter load, a delay from 2.6 ns to 76.3 ms is achieved in 0.8 /spl mu/m CMOS technology. Based on a CMOS thyristor concept, the delay value of the proposed element can be varied over a wide range by a control current. The inherent advantage of a CMOS thyristor in low voltage domains enables this delay element to work down to the supply voltage of 1 V while the threshold voltage of the nMOS and pMOS transistors are 840 mV and -770 mV, respectively. The designed delay value is less sensitive to supply voltage and temperature variation than RC-based or CMOS inverter-based delay elements. Temperature compensation and jitter performance in a noisy environment are also discussed.

Abstract: Issues, challenges, and potential directions for further performance gains beyond 0.1 /spl mu/m CMOS are explored. Gate oxide thickness will soon be tunneling-current limited below 20 /spl Aring/, or roughly 7 atomic layers. V/sub dd/ scaling will slow to accommodate pressure on performance from V/sub t/-nonscaling, pushing CMOS to higher electric fields. Highly abrupt, vertically and laterally nonuniform SUPER-HALO doping profiles will be required for control of short-channel effects in the 0.05 /spl mu/m channel-length regime. More than 6-levels of hierarchical wiring, with the top levels limited only by the speed of EM-wave propagation, are needed to deal with interconnect RC delays. Beyond conventional CMOS, several non-mainstream device alternatives such as SOI, SiGe, and low-temperature CMOS are discussed. The potential performance benefit of each in a CMOS circuit is assessed.