Abstract: Vertically integrated NAND (V-NAND) flash memory is the main data storage in modern handheld electronic devices, widening its share even in the data centers where installation and operation costs are critical. While the conventional scaling rule has been applied down to the design rule of ∼15 nm (year 2013), the current method of increasing device density is stacking up layers. Currently, 176 layer-stacked V-NAND flash memory is available on the market. Nonetheless, increasing the layers invokes several challenges, such as film stress management and deep contact hole etching. Also, there should be an upper bound for the attainable stacking layers (400-500) due to the total allowable chip thickness, which will be reached within 6-7 years. This review summarizes the current status and critical challenges of charge-trap-based flash memory devices, with a focus on the material (floating-gate versus charge-trap-layer), array-level circuit architecture (NOR versus NAND), physical integration structure (two-dimensional versus three-dimensional), and cell-level programming technique (single versus multiple levels). Current efforts to improve fabrication processes and device performances using new materials are also introduced. The review suggests directions for future storage devices based on the ionic mechanism, which may overcome the inherent problems of flash memory devices. This article is protected by copyright. All rights reserved.

Abstract: NAND flash memory shows prominent performance, so it has been used as storage devices of consumer electronics, such as the smart phones and tablet personal computers. As the storage management software of NAND flash memory, the page-level flash translation layer (PLFTL) owns very high I/O access performance for consumer electronics. As an improved version of PLFTL, the demand-based PLFTL selectively keeps active mapping entries in the DRAM (Dynamic Random Access Memory) and the demand-based PLFTL mainly considers the temporal locality of workloads. However, the spatial locality also appears in many workloads. To exploit the temporal locality and spatial locality of workloads, a novel dual locality-based FTL (DL-FTL) is proposed in this paper. DL-FTL uses the sequential cache mapping state table (S-CMST) and sequential physical address cache mapping table (SPA-CMT) to process the sequential requests. To decrease the update counts of translation pages, the mapping entries that are evicted from S-CMST will be written back to NAND flash memory using a batch update strategy. The experimental results show that our proposed DL-FTL raises the cache hit ratio by up to 66.39% and reduces the system response time by up to 21.64% on average, compared with the demand-based PLFTL.

Abstract: Solid-state drive (SSD) gradually dominates in the high-performance storage scenarios. Three-dimension (3D) NAND flash memory owning high-storage capacity is becoming a mainstream storage component of SSD. However, the interferences of the new 3D charge-trap (CT) NAND flash are getting unprecedentedly complicated, yielding to many problems regarding reliability and performance. Alleviating these problems needs to understand the characteristics of 3D CT NAND flash memory deeply. To facilitate such understanding, in this article, we delve into characterizing the performance, reliability, and threshold voltage (Vth) distribution of 3D CT NAND flash memory. We make a summary of these characteristics with multiple interferences and variations and give several new insights and a characterization methodology. Especially, we characterize the skewed (Vth) distribution, (Vth) shift laws, and the exclusive layer variation in 3D NAND flash memory. The characterization is the backbone of designing more reliable and efficient flash-based storage solutions.

Abstract: With the rise of the mobile-centric era, data-driven applications such as the Internet of Things, artificial intelligence, cloud computing, blockchain, and so on are ever increasing. As these applications create unprecedented amounts of data, the technologies used for collecting, processing, and storing them well are becoming more crucial. According to the research in [1], the amount of data we generate has a growth rate of 2.5 times per every four years, and the total amount of data will reach 175 ZB by 2025. Such a “Big Bang” of data means a tremendous demand on storage systems; it is evident that high-capacity and high-performance storage systems will play a key role. Therefore, along with this trend, NAND flash memory technology has continued to evolve to meet high demands. This article covers key technologies for high-density/high-performance NAND flash memory.

Abstract: Flash memory with high operation speed and stable retention performance is in great demand to meet the requirements of big data. In addition, the realisation of ultrafast flash memory with novel functions offers a means of combining heterogeneous components into a homogeneous device without considering impedance matching. This report proposes a 20 ns programme flash memory with 108 self-rectifying ratios based on a 0.65-nm-thick MoS2-channel transistor. A high-quality van der Waals heterojunction with a sharp interface is formed between the Cr/Au metal floating layer and h-BN tunnelling layer. In addition, the large rectification ratio and low ideality factor (n = 1.13) facilitate the application of the MoS2-channel flash memory as a bit-line select transistor. Finally, owing to the ultralow MoS2/h-BN heterojunction capacitance (50 fF), the memory device exhibits superior performance as a high-frequency (up to 1 MHz) sine signal rectifier. These results pave the way toward the potential utilisation of multifunctional memory devices in ultrafast two-dimensional NAND-flash applications.

Abstract: The ESP series of electronics chips and boards are one of the most popular IoT devices and are dominant in the low-end IoT market. Unlike traditional electronic devices, in order to maintain the compact size, ESP devices are not equipped with a hard disk drive. Instead, their microcontrollers are tightly coupled with flash storage chips, which are the high-value targets from a digital forensics (DFs) perspective. To retrieve forensically intact evidences from these devices’ flash storage chips, investigators must be very careful in extracting data, in case the microcontrollers are activated unintentionally, which may allow the microcontroller to write something to the flash storage chips—the result will be unacceptable at court because the data integrity is concerned. This article is trying to solve this challenge, especially for tiny devices, by providing a standard process, utilizing 3D-printed enclosures, spring pins, and cold soldering techniques. The proposals here for the ESP series of IoT devices can be further explored in other IoT devices in the field of DFs.

Abstract: Various core memory devices have been proposed for utilization in future in-memory computing technology featuring high energy efficiency. Flash memory is considered as a viable choice owing to its high integration density, stability, and reliability, which has been verified by commercialized products. However, its high operating voltage and slow operation speed issues caused by the tunneling mechanism make its adoption in in-memory computing applications difficult. In this paper, we introduce a dual-mode memory device named “ferro-floating memory”, fabricated using van der Waals (vdW) materials (h-BN, MoS2, and α-In2Se3). The vdW material, α-In2Se3, acts as a polarization control layer for the ferroelectric memory operation and charge storage layer for the conventional flash memory operation. Compared to the tunneling-based memory operation, the ferro-floating memory operates 1.9 and 3.3 times faster at 6.7 and 5.8 times lower operating voltages for programming and erasing operations, respectively. The dual-mode operation improves the linearity of conductance change by 5 times and the dynamic range by 48% through achieving conductance variation regions. Furthermore, we assess the effects of the variation in device operating voltage on neural networks and suggest a memory array operating scheme for maximizing the networks' performance through various training/inference simulations.

Abstract: The advancement of nonvolatile memory (NVM) technology reduces the cost-per-unit of solid-state drives (SSDs). Flash memory-based SSDs have become ubiquitous because they provide better performance and energy efficiency than hard disk drives. However, it suffers from wear-out problems caused by the out-of-place updates that limit its lifetime. Log-structured merge tree (LSM-tree) is a level-based data structure that is widely used in many database systems because it eliminates the random write operations to the storage devices. By transferring the random write operations into sequential write operations, the write performance of hard disk drives can be improved. However, LSM-tree is not efficient for SSDs because it is not aware of the access characteristics of flash memory. Moreover, the level-based indexing strategy of the LSM-tree significantly shortens the lifetime of SSDs because the data must be frequently updated due to the compaction operations between different levels. In contrast to many previous works that focus on alleviating the write amplification on SSDs for the database systems implemented by LSM-tree, we propose LLSM, a lifetime-aware wear-leveling for LSM-tree on NAND flash memory with open-channel SSD. By considering the data access frequency of the LSM-tree between different levels, LLSM rethinks the block allocation strategy during the compaction to evenly erase all the blocks of SSD storage devices, prolonging the SSD lifetime. Moreover, a proactive swapping strategy is designed to reorganize the data blocks for resolving the potential wear-leveling issues caused by the behaviors of the LSM-tree. The extensive experiments show that the results of lifetime improvement are encouraging.

Abstract: Three-dimensional (3D) flash memory is an emerging memory technology that enables a number of improvements to conventional planar NAND flash memory, including larger capacity, less program disturb, and lower access latency. Despite these advantages, 3D flash memory brings a number of new challenges. First, in 3D flash memory, NAND strings punch through multiple stacked layers to form the 3D infrastructure. Current etching process is unable to manufacture perfect channels with identical feature size. Second, with more stacked layers, the cell current in 3D flash memory is only 20% compared to planar flash memory, making it difficult to give a reliable sensing margin. These issues are affected by process variation, and they pose threats to the integrity of data stored in 3D flash memory. This article present PVSensing , a process-variation-aware space allocation strategy for open-channel SSD with 3D charge-trap flash memory. PVSensing is a novel hardware and file system interface that can transparently allocate physical space in the presence of process variation. PVSensing utilizes the rich functionalities provided by the system infrastructure of open-channel SSD to reduce the uncorrectable bit errors. Three reliability enhancement strategies (i.e., the adaptive creation of fault cubes, the physical block mining, and the live migration of write requests) are proposed. We demonstrate the viability of the proposed technique using a set of extensive experiments. Experimental results show that PVSensing can effectively reduce uncorrectable bit errors, and improve the reliability of critical data with negligible extra erase operations in comparison with representative schemes.

Abstract: ULTRARAM is a nonvolatile memory with the potential to achieve fast, ultralow-energy electron storage in a floating gate accessed through a triple-barrier resonant tunneling heterostructure. Here its implementation is reported on a Si substrate; a vital step toward cost-effective mass production. Sample growth using molecular beam epitaxy commences with deposition of an AlSb nucleation layer to seed the growth of a GaSb buffer layer, followed by the III–V memory epilayers. Fabricated single-cell memories show clear 0/1 logic-state contrast after ≤10 ms duration program/erase pulses of ≈2.5 V, a remarkably fast switching speed for 10 and 20 µm devices. Furthermore, the combination of low voltage and small device capacitance per unit area results in a switching energy that is orders of magnitude lower than dynamic random access memory and flash, for a given cell size. Extended testing of devices reveals retention in excess of 1000 years and degradation-free endurance of over 107 program/erase cycles, surpassing very recent results for similar devices on GaAs substrates.

Abstract: The size of the memory market is expected to continue to expand due to the digital transformation triggered by the fourth industrial revolution. Among various types of memory, NAND flash memory has established itself as a major data storage medium based on excellent cell characteristics and manufacturability; as such, the demand for increasing the bit density and the performance has been rapidly increasing. In this paper, we will review the device operation algorithm and techniques to improve the cell characteristics and reliability in terms of optimization of individual program, read and erase operation, and system level performance.

Abstract: The detection of temporal correlations among event-driven data streams is widely demanded in data-intensive applications such as edge computing. In this work, temporal correlation detection is enabled by the combination of 3D NAND flash and in-memory computing. Different from mathematical scheme by covariance matrix calculation, here the detection is implemented by exploiting the physical process of charge tunneling and accumulation. Thus the intrinsic charge-trapping dynamics in 3D NAND flash can be leveraged to perform in-memory computing. The computing results are stored and imprinted in the threshold voltages of the 3D NAND device array, enabling co-existence of computation and storage in the same devices. On this basis, the validation of temporal correlation detection further paves the way for 3D NAND application in high-level non-von Neumann computing.

Abstract: Triple-level cell NAND flash memory is widely used today due to its higher storage density and capacity. However, with the increase in the storage density, lower reliability results in more read times for flash memory and significantly reduces the read performance. In order to avoid unnecessary read operations, this article proposes a hard decision–soft decoding method called location information-assisted decoding (LIAD) method, which determines the additional information required for decoding by mutual information, and then transmits the required information to correct the log-likelihood ratio (LLR). Different from the conventional LLR correction algorithm, this method does not require additional read operations and correct data. Only using sensing results, our method can reduce uncorrectable error bit rate (UBER) by up to 99%, and the system read latency under SSDsim (Hu et al. 2011) simulation can be reduced by up to 53%.

Abstract: As a strong candidate for computing in memory, 3D NAND flash memory has attracted great attention due to the high computing efficiency, which outperforms the conventional von-Neumann architecture. To ensure 3D NAND flash memory is truly integrated in the computing in a memory chip, a new candidate with high density and a large on/off current ratio is now urgently needed. Here, we first report that 3D NAND flash memory with a high density of multilevel storage can be realized in a double-layered Si quantum dot floating-gate MOS structure. The largest capacitance–voltage (C-V) memory window of 6.6 V is twice as much as that of the device with single-layer nc-Si quantum dots. Furthermore, the stable memory window of 5.5 V can be kept after the retention time of 105 s. The obvious conductance–voltage (G-V) peaks related to the charging process can be observed, which further confirms that the multilevel storage can be realized in double-layer Si quantum dots. Moreover, the on/off ratio of 3D NAND flash memory with a nc-Si floating gate can reach 104, displaying the characteristic of a depletion working mode of an N-type channel. The memory window of 3 V can be maintained after 105 P/E cycles. The programming and erasing speed can arrive at 100 µs under the bias of +7 V and −7 V. Our introduction of double-layer Si quantum dots in 3D NAND float gating memory supplies a new way to the realization of computing in memory.

Abstract: A novel encrypted Computing-in-Memory (eCIM) architecture is proposed based on 55nm NOR Flash memory technology, wherein the current fluctuations caused by random telegraph noise (RTN) in flash cells are utilized as the intrinsic encryption source. Furthermore, aiming at the low-power consumption with high bit-density, the near-subthreshold region of the flash cell is used for 2-bit/cell operation. It is demonstrated that, in the designed 32-bit floating-point (FP) calculation architecture, ultra-low power dissipation (0.24 pJ/bit) can be achieved with high calculation accuracies after the decryption.

Abstract: Flash memory has been developed with bit density improvement, technology scaling, and 3-D stacking. With this trend, its reliability has been significantly degraded. Error correction code (ECC), such as low-density parity code (LDPC), which has strong error correction capability, has been deployed to solve this problem. However, one of the critical issues of LDPC is that it would introduce a long decoding latency on devices with low reliability. In this case, tail latency would happen, which will significantly impact the quality of service. In this work, a set of smart refresh schemes is proposed to optimize the tail latency. The basic idea of the work is to refresh data when the accessed data have a long decoding latency. Two smart refresh schemes are proposed for this work. The first refresh scheme is designed to refresh data with a long access latency when they are accessed several times. The second refresh scheme is designed to periodically check data with an extremely long access latency and refresh them. To further optimize the refresh overhead caused by the above refresh schemes, a dual-ECC-based refresh scheme is proposed. Besides, a mathematical model for all proposed schemes is constructed to clarify the benefit of each scheme. The experimental results show that the proposed schemes can significantly improve the tail latency with acceptable overhead. What is more, the access performance is well maintained compared with the state-of-the-art work.

Abstract: In this article, we provide an analytical model for the total ionizing dose (TID) effects on the bit error statistics of commercial flash memory chips. We have validated the model with experimental data collected by irradiating several commercial NAND flash memory chips from different technology nodes. We find that our analytical model can project bit errors at higher TID values [~20 krad (Si)] from measured data at lower TID values [<1 krad (Si)]. Based on our model and the measured data, we have formulated basic design rules for using a commercial flash memory chip as a dosimeter. We discuss the impact of NAND chip-to-chip variability, noise margin, and the intrinsic errors on the dosimeter design using detailed experimentation.

Abstract: In this paper, we introduce key cell operation technologies to overcome scale-down issues in 3D NAND Flash memory. More specifically, we review several program / erase / read techniques to mitigate WL interference and retention problem for more reliable cell operation.

Abstract: In this paper, we explore the data recovery procedures from ${e} \cdot $ MMCs. The ${e} \cdot $ MMC is one of the “managed” flash memory devices that are popularly used in modern digital devices as their storage media. The ${e} \cdot $ MMC, which consists of flash memory and the flash memory controller, optimizes the data input/output between the host device and the non-volatile memory through its standardized protocol. Its standardized structure and protocol makes forensic physical data acquisition simpler than handling the raw flash memory. However, its secure data purging features, such as Secure Erase and Sanitize, make data recovery from ${e} \cdot $ MMC a challenging task. In this research, we investigate inside the ${e} \cdot $ MMCs, and evaluate advanced data recovery procedures. By reverse engineering the structures of ${e} \cdot $ MMCs and accessing the internal flash memory, we discover that securely erased data is still recoverable from the internal flash memory. In some models, more than 99% of the securely erased data can still be recoverable by accessing the flash memory inside the ${e} \cdot $ MMCs. The data extraction method, along with experimental data recovery evaluation, will be explored in this paper.

Abstract: The quantitative characteristics of traps created in the bandgap-engineered tunneling oxide (BE-TOX) layer and block layer after program/erase (P/E) stress-cycling in a 3D NAND flash memory were investigated. The trap spectroscopy by charge injection and sensing technique was used to obtain the distribution of traps in these layers. In the BE-TOX layer, significant traps were generated at 1.3 eV in the nitrogen-doped layer (N1) and increased by 48% in the fresh cell after P/E stress-cycling. The H bonds in the N1 are more likely to break during the stress-cycling and create neutral ≡ SiO^● traps. In the block layer, however, trap generation was negligible after stress-cycling.

Abstract: Three-dimension (3D) NAND flash memory is the preferred storage component of solid-state drive (SSD) for its high ratio of capacity and cost. Optimizing the reliability of modern SSD needs to test and collect a large amount of real-world error data from 3D NAND flash memory. However, the test costs have surged dozens of times as its capacity increases. It's imperative to reduce the costs of testing denser and high-capacity flash memory. To facilitate it, in this paper, we aim to enable reproducing error data efficiently for 3D NAND flash memory. We use a conditional generative adversarial network (cGAN) to learn the error distribution with multiple interferences and generate diverse error data comparable to the real-world. Evaluation results demonstrate it is feasible and efficient for error generation with cGAN.

Abstract: The density and cost-effectiveness of flash memory chips continue to increase, driven by: (a) The continuous physical scaling of memory cells in a single layer; (b) The vertical stacking of multiple layers; and (c) Logical scaling through storing multiple bits of information in a single memory cell. The physical properties of flash memories impose disproportionate latency and energy expenditures to ensure the high integrity of the data during flash memory writes. This paper experimentally explores this disproportionality on state-of-the-art commercial 3D NAND flash memories and introduces EXPRESS—a technique for increasing the energy efficiency of flash memory writes by exploiting the premature termination of the flash write operations. An experimental evaluation shows that EXPRESS reduces energy expenditures by 20–50%, relative to the traditional flash writes, at the cost of a minimal loss in the data integrity (<1%). In addition, we evaluate the effects of the page-to-page variability, program–erase cycling, and data retention on the implementation of EXPRESS, and we propose enhancements to counter these effects.

Abstract: Emerging applications like machine learning in embedded devices (e.g., satellites and vehicles) require huge storage space, which recently stimulates the widespread deployment of large-scale flash memory in IoT devices. However, existing embedded file systems fall short in managing large-capacity storage efficiently for two reasons. First, prior arts store data structures of file systems either in flash or in main memory, which severely magnifies the scarcity of computing and memory resources. Moreover, the fine-grained metadata management in the existing embedded file systems induces significant energy consumption for large-capacity storage. In this paper, we propose a novel embedded file system, ELOFS, to tackle the above issues and manage large-capacity NAND flash on resource-scarce devices. ELOFS is made efficient through three novel techniques. First, we redefine the space management granularity and streamline the metadata to speed up the mounting performance. In addition, we design hybrid file structures to adapt dissimilar access patterns of embedded devices. Furthermore, ELOFS provides opportunities for in-depth cooperation with application-specific systems. We implement ELOFS with Memory Technology Device (MTD) interfaces, and the experimental results show that ELOFS outperforms YAFFS and UBIFS in terms of write, read, and deletions with orders of magnitude reductions on memory footprint and mounting time.

Abstract: The influence of the channel hole remaining ratio ( CHRR ) on the hemi-cylindrical (HC) vertical NAND (VNAND) flash memory was investigated using both simulation and experimental data. Although HC VNAND flash memory is advantageous for increasing lateral memory density, it suffers from nonuniform carrier injection and low program/erase efficiency. In this study, the underlying physics of these disadvantages are discussed in terms of the proposed parameter, CHRR . Finally, based on the analysis, a recessed channel HC VNAND flash memory cell is proposed.