Showing papers on "Flash memory published in 2015"
9 Mar 2015
TL;DR: This paper describes how the threshold voltage distribution of flash memory changes with different retention age - the length of time since a flash cell was programmed, and proposes two new techniques, Retention Optimized Reading and Retention Failure Recovery, which can effectively recover data from otherwise uncorrectable flash errors.
Abstract: Retention errors, caused by charge leakage over time, are the dominant source of flash memory errors. Understanding, characterizing, and reducing retention errors can significantly improve NAND flash memory reliability and endurance. In this paper, we first characterize, with real 2y-nm MLC NAND flash chips, how the threshold voltage distribution of flash memory changes with different retention age — the length of time since a flash cell was programmed. We observe from our characterization results that 1) the optimal read reference voltage of a flash cell, using which the data can be read with the lowest raw bit error rate (RBER), systematically changes with its retention age, and 2) different regions of flash memory can have different retention ages, and hence different optimal read reference voltages. Based on our findings, we propose two new techniques. First, Retention Optimized Reading (ROR) adaptively learns and applies the optimal read reference voltage for each flash memory block online. The key idea of ROR is to periodically learn a tight upper bound, and from there approach the optimal read reference voltage. Our evaluations show that ROR can extend flash memory lifetime by 64% and reduce average error correction latency by 10.1%, with only 768 KB storage overhead in flash memory for a 512 GB flash-based SSD. Second, Retention Failure Recovery (RFR) recovers data with uncorrectable errors offline by identifying and probabilistically correcting flash cells with retention errors. Our evaluation shows that RFR reduces RBER by 50%, which essentially doubles the error correction capability, and thus can effectively recover data from otherwise uncorrectable flash errors.
351 citations
TL;DR: In this article, a dual-gate charge-trap memory device composed of a few-layer MoS2 channel and a three-dimensional (3D) Al2O3/HfO2/Al 2O3 gate stack is presented.
Abstract: Charge-trap memory with high-κ dielectric materials is considered to be a promising candidate for next-generation memory devices. Ultrathin layered two-dimensional (2D) materials like graphene and MoS2 have been receiving much attention because of their fantastic physical properties and potential applications in electronic devices. Here, we report on a dual-gate charge-trap memory device composed of a few-layer MoS2 channel and a three-dimensional (3D) Al2O3/HfO2/Al2O3 charge-trap gate stack. Because of the extraordinary trapping ability of both electrons and holes in HfO2, the MoS2 memory device exhibits an unprecedented memory window exceeding 20 V. Importantly, with a back gate the window size can be effectively tuned from 15.6 to 21 V; the program/erase current ratio can reach up to 10(4), allowing for multibit information storage. Moreover, the device shows a high endurance of hundreds of cycles and a stable retention of ∼ 28% charge loss after 10 years, which is drastically lower than ever reported MoS2 flash memory. The combination of 2D materials with traditional high-κ charge-trap gate stacks opens up an exciting field of nonvolatile memory devices.
254 citations
22 Jun 2015
TL;DR: In this paper, the impact of read disturb errors on NAND NAND flash memory chips was investigated and two new techniques were proposed to mitigate read disturb by dynamically tuning the pass-through voltage on a per-block basis.
Abstract: NAND flash memory reliability continues to degrade as the memory is scaled down and more bits are programmed per cell. A key contributor to this reduced reliability is read disturb, where a read to one row of cells impacts the threshold voltages of unread flash cells in different rows of the same block. Such disturbances may shift the threshold voltages of these unread cells to different logical states than originally programmed, leading to read errors that hurt endurance. For the first time in open literature, this paper experimentally characterizes read disturb errors on state-of-the-art 2Y-nm (i.e., 20-24 nm) MLC NAND flash memory chips. Our findings (1) correlate the magnitude of threshold voltage shifts with read operation counts, (2) demonstrate how program/erase cycle count and retention age affect the read-disturb-induced error rate, and (3) identify that lowering pass-through voltage levels reduces the impact of read disturb and extend flash lifetime. Particularly, we find that the probability of read disturb errors increases with both higher wear-out and higher pass-through voltage levels. We leverage these findings to develop two new techniques. The first technique mitigates read disturb errors by dynamically tuning the pass-through voltage on a per-block basis. Using real workload traces, our evaluations show that this technique increases flash memory endurance by an average of 21%. The second technique recovers from previously-uncorrectable flash errors by identifying and probabilistically correcting cells susceptible to read disturb errors. Our evaluations show that this recovery technique reduces the raw bit error rate by 36%.
201 citations
13 Jun 2015
TL;DR: BlueDBM, a new system architecture which has flash-based storage with in-store processing capability and a low-latency high-throughput inter-controller network, is presented, showing that BlueDBM outperforms aflash-based system without these features by a factor of 10 for some important applications.
Abstract: Complex data queries, because of their need for random accesses, have proven to be slow unless all the data can be accommodated in DRAM. There are many domains, such as genomics, geological data and daily twitter feeds where the datasets of interest are 5TB to 20 TB. For such a dataset, one would need a cluster with 100 servers, each with 128GB to 256GBs of DRAM, to accommodate all the data in DRAM. On the other hand, such datasets could be stored easily in the flash memory of a rack-sized cluster. Flash storage has much better random access performance than hard disks, which makes it desirable for analytics workloads. In this paper we present BlueDBM, a new system architecture which has flash-based storage with in-store processing capability and a low-latency high-throughput inter-controller network. We show that BlueDBM outperforms a flash-based system without these features by a factor of 10 for some important applications. While the performance of a ram-cloud system falls sharply even if only 5%~10% of the references are to the secondary storage, this sharp performance degradation is not an issue in BlueDBM. BlueDBM presents an attractive point in the cost-performance trade-off for Big Data analytics.
199 citations
20 Aug 2015
TL;DR: WARM is proposed, awrite-hotness aware retention management policy for flash memory, which identifies and physically groups together write-hot data within the flash device, allowing the flash controller to selectively perform retention time relaxation with little cost.
Abstract: Increased NAND flash memory density has come at the cost of lifetime reductions. Flash lifetime can be extended by relaxing internal data retention time, the duration for which a flash cell correctly holds data. Such relaxation cannot be exposed externally to avoid altering the expected data integrity property of a flash device. Reliability mechanisms, most prominently refresh, restore the duration of data integrity, but greatly reduce the lifetime improvements from retention time relaxation by performing a large number of write operations. We find that retention time relaxation can be achieved more efficiently by exploiting heterogeneity in write-hotness, i.e., the frequency at which each page is written. We propose WARM, a write-hotness aware retention management policy for flash memory, which identifies and physically groups together write-hot data within the flash device, allowing the flash controller to selectively perform retention time relaxation with little cost. When applied alone, WARM improves overall flash lifetime by an average of 3.24x over a conventional management policy without refresh, across a variety of real I/O workload traces. When WARM is applied together with an adaptive refresh mechanism, the average lifetime improves by 12.9x, 1.21x over adaptive refresh alone.
150 citations
Patent•
22 May 2015TL;DR: In this article, a storage controller for determining an amount of data to be sent to a flash memory apparatus for storage comprises a communications interface for communicating with the flash memory equipment and a processor.
Abstract: A storage controller for determining an amount of data to be sent to a flash memory apparatus for storage comprises a communications interface for communicating with the flash memory apparatus and a processor. The flash memory apparatus comprises a block including a plurality of pages. And at least one of the pages is unavailable for storage. The processor is configured to receive information of the block sent by the flash memory apparatus, wherein the information includes capacity of one or more unavailable pages in the block. And then, the processor determines an available capacity of the block, based on the information and a total capacity of the block. Further, the processor obtains data to be sent to the flash memory apparatus, wherein an amount of the data is equal to the available capacity of the block. At last, the processor sends the data to the flash memory apparatus.
147 citations
Patent•
15 Dec 2015
TL;DR: In this paper, a method of managing NAND flash memory in an electronic device whereby system performance of the electronic device is minimally impacted is disclosed, which comprises collecting files that are marked for deletion or truncation; monitoring an activity level of the EH device; monitoring a total size of the list of files that were marked for deleting or truncating; determining if the electronic devices is idle; and trimming the flash memory of the Electronic device if predetermined criteria are met.
Abstract: A method of managing NAND flash memory in an electronic device whereby system performance of the electronic device is minimally impacted is disclosed. The method comprises collecting files that are marked for deletion or truncation; monitoring an activity level of the electronic device; monitoring a total size of the list of files that are marked for deletion or truncation; determining if the electronic device is idle; and trimming the flash memory of the electronic device if predetermined criteria are met.
96 citations
Patent•
17 Dec 2015
TL;DR: In this paper, a miniature barcode reading module for an electronic device minimizes the size of the memory of the processor die allowing the module to be used in small form factor electronic devices.
Abstract: A miniature barcode reading module for an electronic device minimizes the size of the memory of the processor die allowing the module to be used in small form factor electronic devices. The module may include an image sensor package operative to scan a barcode and a processor die coupled to the image sensor package. The processor die may include a processor, a memory, a flash memory, a plurality of barcode scanning algorithms loaded into the flash memory, and an image capture port operatively connected to the image sensor package. Barcode scanning firmware can determine if a barcode decoding algorithm is loaded in the memory, determine if the loaded barcode decoding algorithm is a correct barcode decoding algorithm or an incorrect barcode decoding algorithm, unload an incorrect barcode decoding algorithm from the memory, and load a correct barcode decoding algorithm into the memory.
94 citations
TL;DR: For the first time, nonvolatile charge-trap memory devices, based on field-effect transistors with large hysteresis, consisting of a few-layer black phosphorus channel and a three dimensional (3D) Al2O3/HfO2/Al2 O3 charge- trap gate stack are shown.
Abstract: Atomically thin layered two-dimensional materials, including transition-metal dichacolgenide (TMDC) and black phosphorus (BP), (1) have been receiving much attention, because of their promising physical properties and potential applications in flexible and transparent electronic devices . Here, for the first time we show non-volatile chargetrap memory devices, based on field-effect transistors with large hysteresis, consisting of a few-layer black phosphorus channel and a three dimensional (3D) Al2O3 /HfO2 /Al2O3 charge-trap gate stack. An unprecedented memory window exceeding 12 V is observed, due to the extraordinary trapping ability of HfO2. The device shows a high endurance and a stable retention of ?25% charge loss after 10 years, even drastically lower than reported MoS2 flash memory. The high program/erase current ratio, large memory window, stable retention and high on/off current ratio, provide a promising route towards the flexible and transparent memory devices utilising atomically thin two-dimensional materials. The combination of 2D materials with traditional high-k charge-trap gate stacks opens up an exciting field of nonvolatile memory devices.
87 citations
TL;DR: In this article, photochromic spiropyran-based salts SP1 and SP2 were used as light-sensitive components of OFET-based nonvolatile optical memory elements.
Abstract: Here we applied photochromic spiropyran-based salts SP1 and SP2 as light-sensitive components of OFET-based non-volatile optical memory elements. Electrooptical programming by applying simultaneously light bias and gate (programming) voltage allowed us to demonstrate wide memory windows, high programming speeds (programming time of 0.5–20 ms), and good retention characteristics of the devices. It is remarkable that a minor difference in the molecular structures of the used spiropyran-based salts (the hydrogen atom in the structure of SP1 is replaced with the NO2 group in SP2) altered completely the behavior of the devices. Thus, OFETs comprising interlayers of the spiropyran-based salt SP1 showed a reversible photoelectrical switching which is characteristic for flash memory elements with good write–read–erase cycling stability. In contrast, devices based on the spiropyran-based salt SP2 demonstrated irreversible switching and operated as read-only memory (ROM). Both types of devices revealed the formation of multiple distinct electrical states thus resembling the behavior of multibit memory elements capable of high-density information storage.
72 citations
TL;DR: In this article, a top-gated nanowire molecular flash memory has been fabricated with redox-active molecules and different molecules with one and two redox centers have been tested.
Abstract: In this work, high-performance top-gated nanowire molecular flash memory has been fabricated with redox-active molecules. Different molecules with one and two redox centers have been tested. The flash memory has clean solid/molecule and dielectric interfaces, due to the pristine molecular self-assembly and the nanowire device self-alignment fabrication process. The memory cells exhibit discrete charged states at small gate voltages. Such multi-bit memory in one cell is favorable for high-density storage. These memory devices exhibit fast speed, low power, long memory retention, and exceptionally good endurance (>109 cycles). The excellent characteristics are derived from the intrinsic charge-storage properties of the protected redox-active molecules. Such multi-bit molecular flash memory is very attractive for high-endurance and high-density on-chip memory applications in future portable electronics.
TL;DR: The results prove that the silicon-based ferroelectric tunnel junction is a very promising candidate for application in future non-volatile memories.
Abstract: The quest for solid state non-volatility memory devices on silicon with high storage density, high speed, low power consumption has attracted intense research on new materials and novel device architectures. Although flash memory dominates in the non-volatile memory market currently, it has drawbacks, such as low operation speed, and limited cycle endurance, which prevents it from becoming the "universal memory". In this report, we demonstrate ferroelectric tunnel junctions (Pt/BaTiO3/La0.67Sr0.33MnO3) epitaxially grown on silicon substrates. X-ray diffraction spectra and high resolution transmission electron microscope images prove the high epitaxial quality of the single crystal perovskite films grown on silicon. Furthermore, the write speed, data retention and fatigue properties of the device compare favorably with flash memories. The results prove that the silicon-based ferroelectric tunnel junction is a very promising candidate for application in future non-volatile memories.
TL;DR: Enterprise servers use flash memory based solid state drives as a high-performance alternative to hard disk drives to store persistent data, but recent increases in flash density have also boosted the cost of these drives.
Abstract: Servers use flash memory based solid state drives (SSDs) as a high-performance alternative to hard disk drives to store persistent data. Unfortunately, recent increases in flash density have also b...
TL;DR: This paper proposes a novel Demand-based block-level Address mapping scheme with a two-level Caching mechanism (DAC) for large-scale NAND flash storage systems to reduce RAM footprint without excessively compromising system response time.
Abstract: The density of flash memory chips has doubled every two years in the past decade and the trend is expected to continue. The increasing capacity of NAND flash memory leads to large RAM footprint on address mapping management. This paper proposes a novel Demand-based block-level Address mapping scheme with a two-level Caching mechanism (DAC) for large-scale NAND flash storage systems. The objective is to reduce RAM footprint without excessively compromising system response time. In our technique, the block-level address mapping table is stored in fixed pages (called the translation pages) in the flash memory. Considering temporal locality that workloads exhibit, we maintain one cache in RAM to store the on-demand address mapping entries. Meanwhile, by exploring both spatial locality and access frequency of workloads with another two caches, the second-level cache is designed to cache selected translation pages. In such a way, both the most-frequently-accessed and sequentially accessed address mapping entries can be stored in the cache so the cache hit ratio can be increased and the system response time can be improved. To the best of our knowledge, this is the first work to reduce the RAM cost by employing the demand-based approach on block-level address mapping schemes. The experiments have been conducted on a real embedded platform. The experimental results show that our technique can effectively reduce the RAM footprint while maintaining similar average system response time compared with previous work.
TL;DR: The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.
Abstract: Electret and organic floating-gate memories are next-generation flash storage mediums for printed organic complementary circuits. While each flash memory can be easily fabricated using solution processes on flexible plastic substrates, promising their potential for on-chip memory organization is limited by unreliable bit operation and high write loads. We here report that new architecture could improve the overall performance of organic memory, and especially meet high storage for multi-level operation. Our concept depends on synergistic effect of electrical characterization in combination with a polymer electret (poly(2-vinyl naphthalene) (PVN)) and metal nanoparticles (Copper). It is distinguished from mostly organic nano-floating-gate memories by using the electret dielectric instead of general tunneling dielectric for additional charge storage. The uniform stacking of organic layers including various dielectrics and poly(3-hexylthiophene) (P3HT) as an organic semiconductor, followed by thin-film coating using orthogonal solvents, greatly improve device precision despite easy and fast manufacture. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as high-k blocking dielectric also allows reduction of programming voltage. The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.
16 Feb 2015
TL;DR: This work proposes an implicit data compression approach as a complement to conventional explicit data compression that aims to increase the number of sectors per flash memory page and derives a set of mathematical formulations that can quantitatively estimate flash memory physical damage reduction gain.
Abstract: Although data compression can benefit flash memory lifetime, little work has been done to rigorously study the full potential of exploiting data compressibility to improve memory lifetime. This work attempts to fill this missing link. Motivated by the fact that memory cell damage strongly depends on the data content being stored, we first propose an implicit data compression approach (i.e., compress each data sector but do not increase the number of sectors per flash memory page) as a complement to conventional explicit data compression that aims to increase the number of sectors per flash memory page. Due to the runtime variation of data compressibility, each flash memory page almost always contains some unused storage space left by compressed data sectors. We develop a set of design strategies for exploiting such unused storage space to reduce the overall memory physical damage. We derive a set of mathematical formulations that can quantitatively estimate flash memory physical damage reduction gained by the proposed design strategies for both explicit and implicit data compression. Using 20nm MLC NAND flash memory chips, we carry out extensive experiments to quantify the content dependency of memory cell damage, based upon which we empirically evaluate and compare the effectiveness of the proposed design strategies under a wide spectrum of data compressibility characteristics.
Patent•
4 Aug 2015
TL;DR: In this article, the authors present a set of systems and methods for increasing the operational efficiency and extending the estimated operational lifetime of a flash memory storage device (and its component flash memory chips, LUNs and blocks of flash memory).
Abstract: The present invention includes embodiments of systems and methods for increasing the operational efficiency and extending the estimated operational lifetime of a flash memory storage device (and its component flash memory chips, LUNs and blocks of flash memory) by monitoring the health of the device and its components and, in response, adaptively tuning the operating parameters of flash memory chips during their operational lifetime, as well as employing other less extreme preventive measures in the interim, via an interface that avoids the need for direct access to the test modes of the flash memory chips. In an offline characterization phase, "test chips" from a batch of recently manufactured flash memory chips are used to simulate various usage scenarios and measure the performance effects of writing and attempting to recover (read) test patterns written with different sets of operating parameters over time (simulating desired retention periods).
24 May 2015
TL;DR: In this paper, a commercial NOR flash memory array is modified to enable high-precision tuning of individual floating-gate cells for analog computing applications, and the modified array area per cell in a 180 nm process is about 1.5 μm2.
Abstract: We have modified a commercial NOR flash memory array to enable high-precision tuning of individual floating-gate cells for analog computing applications. The modified array area per cell in a 180 nm process is about 1.5 μm2. While this area is approximately twice the original cell size, it is still at least an order of magnitude smaller than in state-of-the-art analog circuit implementations. The new memory cell arrays have been successfully tested, in particular confirming that each cell may be automatically tuned, with ∼1% precision, to any desired subthreshold readout current value within an almost three-orders-of-magnitude dynamic range, even using an unoptimized tuning algorithm. Preliminary results for a four-quadrant vector-by-matrix multiplier, implemented with the modified memory array, gate-coupled with additional peripheral floating-gate transistors, show highly linear transfer characteristics over a broad range of input currents.
17 Apr 2015
TL;DR: An efficient page-level FTL, named TPFTL, is proposed, which employs two-level LRU lists to organize cached mapping entries to minimize the extra operations in the flash translation layer.
Abstract: Flash-based solid state disks (SSDs) have been very popular in consumer and enterprise storage markets due to their high performance, low energy, shock resistance, and compact sizes. However, the increasing SSD capacity imposes great pressure on performing efficient logical to physical address translation in a page-level flash translation layer (FTL). Existing schemes usually employ a built-in RAM cache for storing mapping information, called the mapping cache, to speed up the address translation. Since only a fraction of the mapping table can be cached due to limited cache space, a large number of extra operations to flash memory are required for cache management and garbage collection, degrading the performance and lifetime of an SSD. In this paper, we first apply analytical models to investigate the key factors that incur extra operations. Then, we propose an efficient page-level FTL, named TPFTL, which employs two-level LRU lists to organize cached mapping entries to minimize the extra operations. Inspired by the models, we further design a workload-adaptive loading policy combined with an efficient replacement policy to increase the cache hit ratio and reduce the writebacks of replaced dirty entries. Finally, we evaluate TPFTL using extensive trace-driven simulations. Our evaluation results show that compared to the state-of-the-art FTLs, TPFTL reduces random writes caused by address translation by an average of 62% and improves the response time by up to 24%.
Patent•
12 Mar 2015
TL;DR: In this paper, an apparatus for communicating data requests received by host devices using one DDR protocol to memory devices using a different DDR protocol is presented, which includes an ONFI communication interface for communicating with a plurality of flash memory devices and a SSD processor coupled to the communication interface.
Abstract: An apparatus for communicating data requests received by host devices using one DDR protocol to memory devices using a different DDR protocol is presented. The apparatus includes an ONFI communication interface is for communicating with a plurality of flash memory devices and a SSD processor coupled to the communication interface. The SSD processor receives a first signal from a host device corresponding to a first DDR protocol to access DRAM, stores the first signal upon receipt in a data buffer of a plurality of data buffers resident on the apparatus, converts the first signal into a second signal using an ONFI standard, transmits the configured second signal to one of the plurality of flash memory devices corresponding to a second DDR protocol, and receives data from the flash memory device, where the data is converted into signals corresponding to the first DDR4 protocol for communication back to the host device.
TL;DR: This paper proposes an algorithm that uses a limited number of rereads to characterize the noise distribution and recover the stored information, and attempts to find a read threshold minimizing bit error rate and derives an expression for the resulting codeword error rate.
Abstract: A primary source of increased read time on nand flash comes from the fact that, in the presence of noise, the flash medium must be read several times using different read threshold voltages for the decoder to succeed. This paper proposes an algorithm that uses a limited number of rereads to characterize the noise distribution and recover the stored information. Both hard and soft decoding are considered. For hard decoding, this paper attempts to find a read threshold minimizing bit error rate (BER) and derives an expression for the resulting codeword error rate. For soft decoding, it shows that minimizing BER and minimizing codeword error rate are competing objectives in the presence of a limited number of allowed rereads, and proposes a tradeoff between the two. The proposed method does not require any prior knowledge about the noise distribution but can take advantage of such information when it is available. Each read threshold is chosen based on the results of previous reads, following an optimal policy derived through a dynamic programming backward recursion. The method and results are studied from the perspective of an SLC Flash memory with Gaussian noise, but this paper explains how the method could be extended to other scenarios.
TL;DR: In this article, a spin-coated close-packed CdSe/ZnS quantum dots (QDs) monolayer was proposed for UV-manipulated photonic nonvolatile memory.
Abstract: Light-responsive memory, in which the writing, reading and erasing processes are sensitive to light signals, has its own niche for civilian and military applications. However, the control of memory properties with ultraviolet (UV) light is difficult since the common charge trapping layer of flash memory is insensitive to UV light signals. Here, we reported a novel design of UV-manipulated photonic nonvolatile memory based on a spin-coated close-packed CdSe/ZnS quantum dots (QDs) monolayer. Our devices display remarkable UV-induced detrapping behavior and UV-controlled persistent threshold voltage (Vth) shifts of programmed or erased states. The electrically programmed flash memory was even erased by low intensity UV light without an additional external electric field within 1 s, which is superior to the traditional silicon-based erasable programmable read only memory (EPROM). With an advance in the unique UV-detrapping effect of this novel structure, UV-tunable complementary inverters constructed from p-channel and n-channel flash memory have further been demonstrated. The UV tunable charge trapping/detrapping facilitates the creation of a new class of multifunctional optoelectronic memory devices.
TL;DR: The characteristics of PUFs, such as their unclonability, uncontrollability, unpredictability, and robustness, are investigated using fabricated flash memory devices and it is shown that the unpredictability is induced by variations in the gate dielectric thickness.
Abstract: Flash memory devices are investigated to confirm their application as physically unclonable functions (PUFs). Inherent fluctuations in the characteristics of flash memory devices, even with identical fabrication processes, produce different outputs, which are useful for device fingerprints. A difference in programming/erasing efficiency arises from a widely distributed threshold voltage. However, statistical fluctuations in the threshold voltage represent an advantage for PUF applications. The characteristics of PUFs, such as their unclonability, uncontrollability, unpredictability, and robustness, are investigated using fabricated flash memory devices. A simulation study is performed to support the experimental results and to show that the unpredictability is induced by variations in the gate dielectric thickness.
Patent•
30 Jun 2015TL;DR: In this paper, the authors propose to store user data and metadata in persistent storage in the event of a power failure and then to recover such stored data when the power is restored.
Abstract: Embodiments of the technology relate to storing user data and metadata in persistent storage in the event of a power failure and then recovering such stored data and metadata when power is restored.
TL;DR: In this paper, the level of carbon incorporated into a GeSbTe (GST) film that is needed to reduce the RESET current of phase change memory (PCM) devices was determined.
Abstract: Phase Change Memory (PCM) has been proposed for use as a substitute for flash memory to satisfy the huge demands for high performance and reliability that promise to come in the next generation. In spite of its high scalability, reliability, and simple structure, high writing current, e.g., RESET current, has been a significant obstacle to achieving a high density in storage applications and the low power consumption required for use in mobile applications. We report herein on an attempt to determine the level of carbon incorporated into a GeSbTe (GST) film that is needed to reduce the RESET current of PCM devices. The crystal structure of the film was transformed into an amorphous phase by carbon doping, the stability of which was enhanced with increasing carbon content. This was verified by the small grain size and large band gap that are typically associated with carbon. The increased level of C-Ge covalent bonding is responsible for these enhancements. Thus, the resistance of the carbon doped Ge2Sb2Te...
19 Mar 2015
TL;DR: This paper presents 28nm eFlash macros for automotive with four key features, a 28nm split-gate (SG)-MONOS cell array with temperature-adjusted overdrive wordline (WL) voltage control to realize both 200MHz random access and more than 10× longer TDDB lifetime of WL drivers.
Abstract: Accelerated advances in automotive technology, such as sophisticated real-time engine controls for higher fuel efficiency and advanced driver-assistance systems (ADAS), are expanding the application range of Flash MCUs, microcontrollers with embedded Flash memory (eFlash). In addition to consistent demands for faster random access, shorter rewrite time and larger memory capacity in eFlash, there are increasingly intense requirements for robust operations and high data reliability under extremely high junction temperature (T i ,) of 170°C. On the other hand, along with device scaling beyond 40nm generation, the reliability of eFlash systems is constrained by not only eFlash memory cells but also peripheral transistors and metal interconnections. As oxide films in transistor devices and between metal interconnections are getting thinner, their time-dependent dielectric breakdown (TDDB) lifetime is critically degraded, which poses a great challenge in advanced eFlash design.
Journal Article•
TL;DR: In this work, high-performance top-gated nanowire molecular flash memory has been fabricated with redox-active molecules, which are attractive for high-endurance and high-density on-chip memory applications in future portable electronics.
Abstract: In this work, high-performance top-gated nanowire molecular flash memory has been fabricated with redox-active molecules. Different molecules with one and two redox centers have been tested. The flash memory has clean solid/molecule and dielectric interfaces, due to the pristine molecular self-assembly and the nanowire device self-alignment fabrication process. The memory cells exhibit discrete charged states at small gate voltages. Such multi-bit memory in one cell is favorable for high-density storage. These memory devices exhibit fast speed, low power, long memory retention, and exceptionally good endurance (>10(9) cycles). The excellent characteristics are derived from the intrinsic charge-storage properties of the protected redox-active molecules. Such multi-bit molecular flash memory is very attractive for high-endurance and high-density on-chip memory applications in future portable electronics.
Patent•
1 Jun 2015TL;DR: In this article, a method of programming a flash memory device consists of programming selected memory cells, performing a verification operation to determine whether the memory cells have reached a target program state, and determining a start point of the verification operation based on a programming characteristic associated with a detection of a pass bit during programming of an initial program state.
Abstract: A method of programming a flash memory device comprises programming selected memory cells, performing a verification operation to determine whether the selected memory cells have reached a target program state, and determining a start point of the verification operation based on a programming characteristic associated with a detection of a pass bit during programming of an initial program state.
TL;DR: In this paper, the performance of nonvolatile memory devices with the configuration of indium tin oxide (ITO)/active layer/aluminum (Al) is reported. But the active layer was prepared from the mixed compositions of 2-(4-tert-butylphenyl)-5-(4biphenylyl)-1,3,4-oxadiazole, (PBD) and poly(N-vinylcarbazole) (PVK).
TL;DR: In this paper, a self-assembled monolayer (SAM) functionalization of reduced graphene oxide (rGO) was adopted to form p-type and n-type doped rGO with a wide range of manipulation on work function.
Abstract: Tunable charge-trapping behaviors including unipolar charge trapping of one type of charge carrier and ambipolar trapping of both electrons and holes in a complementary manner is highly desirable for low power consumption multibit flash memory design. Here, we adopt a strategy of tuning the Fermi level of reduced graphene oxide (rGO) through self-assembled monolayer (SAM) functionalization and form p-type and n-type doped rGO with a wide range of manipulation on work function. The functionalized rGO can act as charge-trapping layer in ambipolar flash memories, and a dramatic transition of charging behavior from unipolar trapping of electrons to ambipolar trapping and eventually to unipolar trapping of holes was achieved. Adjustable hole/electron injection barriers induce controllable Vth shift in the memory transistor after programming operation. Finally, we transfer the ambipolar memory on flexible substrates and study their charge-trapping properties at various bending cycles. The SAM-functionalized rGO can be a promising candidate for next-generation nonvolatile memories.