Abstract: A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In an alternative embodiment, a refresh process includes reprogramming the threshold voltage into an allowed state. In the case of a flash memory, a refresh reads a sector of the memory and saves corrected data from the sector in a buffer or another sector. The corrected data from the buffer or other sector can be written back in the original sector, or the corrected data can be left in the other sector with addresses of the original sector being mapped to the other sector. Refresh process for the non-volatile memory can be perform in response to detecting a threshold voltage in a forbidden zone, as part of a power-up procedure for the memory, or periodically with a period on the order of days, weeks, or months. As a further aspect, the allowed states correspond to gray coded digital values so that allowed states that are adjacent in threshold voltage correspond to multibit values that differ in only a single bit. Error detection and correction codes can be used to identify data errors and generate corrected data for refresh operations.

Abstract: We present a device structure of SiO2∕SiN∕Al2O3 (SANOS). The use of a high-k dielectric material, specially Al2O3, in the blocking oxide concentrates the electric fields across the tunnel oxide and SiN, and releases it across the blocking oxide under program and erase mode. This effect leads to lower program and erase voltage as well as faster erase speed than the conventional SiO2∕SiN∕SiO2 (SONOS) device. Moreover, it is shown that the fast erase operation is performed even at a thicker tunnel oxide over 30A where the hole direct tunneling current through the tunnel oxide is reduced significantly and thus the SANOS device has the excellent bake retention.

Abstract: One or more secondary data structures are maintained containing mappings of logical flash memory addresses to physical flash memory addresses. Each secondary data structure has a predetermined capacity of mappings. A master data structure is also maintained containing a pointer to each of the one or more secondary data structures. Additional secondary data structures are allocated as needed to provide capacity for additional mappings. One or more counters associated with each of the one or more secondary data structures, respectively, provides an indication of when each of the one or more secondary data structures reaches the predetermined capacity of mappings.

Abstract: In this paper we propose the MicroHash index, which is an efficient external memory structure for Wireless Sensor Devices (WSDs). The most prevalent storage medium for WSDs is flash memory. Our index structure exploits the asymmetric read/write and wear characteristics of flash memory in order to offer high performance indexing and searching capabilities in the presence of a low energy budget which is typical for the devices under discussion. A key idea behind MicroHash is to eliminate expensive random access deletions. We have implemented MicroHash in nesC, the programming language of the TinyOS [7] operating system. Our trace-driven experimentation with several real datasets reveals that our index structure offers excellent search performance at a small cost of constructing and maintaining the index.

Abstract: The present invention relates to erase and program methods of a flash memory device including MLCs for increasing the program speed. In the erase method according to the present invention, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation.

Abstract: Data are stored in one or more cells of a non-volatile memory, and are refreshed according to a predetermined condition. The data are refreshed either in-place or out-of-place. The condition may be related to the age of the data. Alternatively, the data are refreshed periodically, or when the system that includes the memory boots or dismounts, or according to the type of the data.

Abstract: Techniques for managing data in a non-volatile memory system (e.g., Flash Memory) are disclosed. A controller can use information relating to a host's file system, which is stored by the host on non-volatile memory, to determine if one or more clusters (or sectors with clusters) are currently allocated. The controller can use the information relating to the host's file system to identify when the host is sending data to the next free cluster and to store such data in a sequential format by copying data from other locations in the non-volatile memory.

Abstract: A flash memory system including one or more flash memory devices; the flash memory devices are partitioned into multiple units, at least a first unit and a second unit. A mechanism which allocates the units in combination as a super-unit, reserves at least a portion of a first unit field required for managing the super-unit in the first unit and the mechanism reserves at least a portion of a second unit field required for managing the super-unit in the second unit. Preferably, the first unit field and the second unit field are different unit fields, or the first unit field and the second unit field are the same unit field. Preferably, the flash memory device each support at least two planes, and the first unit and the second unit each belong to a different plane. Alternatively, there are two flash memory devices, and the first unit and the second unit each belong to a different flash memory device.

Abstract: A flash memory that supports N>1-bit programming is managed by, for at least one block of the memory, selecting the value of N to use for the block, designating one or more cells of the block as flag cells, and programming the flag cells to represent the selected value of N. Preferably, N is encoded according to whether the threshold voltages of the flag cells are greater or less than a reference voltage common to all values of N. The other cells of the block then are programmed in accordance with the selected value of N. N and its flag cells are selected when the block is first used to store data. Subsequent to an erasure of the block, a different value of N may be selected.

Abstract: A method and apparatus to decrease the boot time and the hibernate awaken time of a computer system is presented. Static and dynamic configuration data is stored in flash memory. The size of flash memory is selected so that the initialization time of the configuration data stored in the flash memory is approximately equal to the spin-up time of the disk drive where the operating system is stored. During power down or entry into a hibernate mode, the computer system determines the static and dynamic configuration data to be stored in flash memory based on a history of prior uses. Data is also stored in the flash memory during system operation to reduce the number of times the disk drive is spun up. When the computer system is powered up or awakened from hibernation, the configuration data in flash memory is initialized while the disk drive is spinning up.

Abstract: A method of correcting errors of a flash memory comprises steps of modifying the data of a group of memory units, each having a plurality of flash memory cells adapted to erasing data therefrom and writing data therein, checking for the presence or absence of an error of not properly modifying the data of the group of memory units and determining the completion of proper modification of the data of the group of memory units provided that an error is detected and the error can be corrected.

Abstract: A method of manufacturing a split-gate flash memory device is disclosed. On a semiconductor substrate having a plurality of parallel conductive lines, a plurality of doped regions are formed by an ion implantation using the conductive lines as mask. Then, the conductive lines are trimmed for thinning the cover area. Afterward, a composite dielectric layer is formed on the substrate and covers the conductive lines. Finally, a plurality of word lines are formed on the composite dielectric layer.

Abstract: A system (300) and method for performing a simultaneous external read operation during internal programming of a memory device (301) is described. The memory device is configured to store data randomly and includes a source location (305), a destination location (303), a data register (307), and a cache register (309). The data register (307) is configured to simultaneously write data to the destination (303) and to the cache register (309). The system (300) further includes a processing device (107) (e.g., a microprocessor or microcontroller) for verifying an accuracy of any data received through electrical communication with the memory device. The processing device (107) is additionally configured to provide for error correction if the received data are inaccurate, add random data to the data, if required, and then transfer the error-corrected and/or random data modified data back to the destination location (303).

Abstract: A plurality of temperature dependent focal plane arrays operate without a temperature stabilization cooler and/or heater over a wide range of ambient temperatures. Gain, offset and/or bias correction tables are provided in a flash memory in memory pages indexed by the measured temperature of the focal plane arrays. The memory stores a calibration database, which is accessed using a logic circuit which generates a memory page address from a digitized temperature measurement of each of the focal plane array. The calibration database is comprised of an array of bias, gain and offset values for each pixel in the focal plane array for each potential operating temperature over the entire range of potential operating temperatures. The bias, gain and offset data within the database are read out, converted to analog form, and used by analog circuits to correct the focal plane array response. The output of each of the FPAs is multiplexed to a shared processing module and calibration data for each of the FPAs is accessed from the shared processing module.

Abstract: A NAND-type flash memory device has a multi-plane structure. Page buffers are divided into even page buffers and odd page buffers and are driven at the same time. Cells connected to even bit lines within one page and cell connected to odd bit lines within one page are programmed, read and copyback programmed at the same time.

Abstract: A method of storing data by providing a flash memory device including a plurality of memory cells; each of the memory cells is capable of storing data bits. First data bits are stored into memory cells used for storing M bits per cell, the memory cells are allocated to a page of the memory. Second data bits are stored into other memory cells, the other memory cells used for storing N bits per cell are allocated to the page and upon storing of the first data bits and upon storing the second data bits, the page uses at the same time at least one of the memory cells with M bits per cell and at least one of the other memory cells with N bits per cell with N less than M.

Abstract: A low voltage of the order of or one to three volts instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero (WLO) immediately adjacent to the source (SGS) or drain side select gate of a NAND flash device (100) to reduce or prevent the shifting of threshold voltage of the memory cells coupled to word line zero during the programming cycles of the different cells of the NAND strings. This may be implemented in any one of a variety of different self boosting schemes including erased areas self boosting and local self boosting schemes.

Abstract: Provided is a secure digital memory card for extension of function, including: a flash memory installed in a host device and storing data generated by the host device; a controller controlling an access interface to the flash memory; a radio frequency circuit performing functions of a contactless integrated circuit card and a contactless integrated circuit card reader through a wireless interface control of the controller; an antenna unit connected to the radio frequency circuit to perform a function of a transmission and reception antenna; and a contact integrated circuit card adapter performing the function of the contact integrated circuit card reader through a wire interface control of the controller.

Abstract: An address at which a writing error occurs is held, and after a completion of a series of writings, the data of the held address is read. Then, a faulty-block processing is performed only for the addresses, for which it is determined that retry of writing is required, thereby preventing an increase of faulty-blocks. This can suppress the problem that when a writing is performed in a particular flash memory, a writing error frequently occurs and a large number of faulty blocks occur.

Abstract: A flash memory system includes a flash controller for controlling operation of at least two flash memory devices. A page buffer is allocated within each flash memory device, such that one page buffer functions as a designated target buffer and another page buffer functions as a mirror buffer. The flash controller transmits the page data to two flash memory devices simultaneously, such that no backup of the page data is required to be kept in the flash controller. Hence, there is no delay in writing the next page data from a host computer to the flash controller.

Abstract: A system and method for implementing a flash memory system. The flash memory system includes a processor and at least one flash memory device. The at least one flash memory device includes a plurality of partitions. As a result, the flash memory system can utilize the multiple partitions to provide multiple functions such as an AutoRun feature.

Abstract: A flash memory device for performing a bad block management and a method of performing bad block management are implemented in hardware level. During a booting procedure of a flash memory device, a bad block-mapping table stored in a predetermined block of memory cell array unit or other nonvolatile memory is stored in a bad block mapping register via a bad block-mapping table loader. An address selector receives a logical address from an external device and compares the logical address with a bad block address stored in the bad block mapping register. A bad block-state controller determines a count number of a re-mapping mark and outputs a re-mapping mark flag to the address selector. The address selector selects a logical address or a bad block address received from the bad block mapping register as a physical address and outputs the physical address to the memory cell array unit.

Abstract: An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the operation currently being executed is discontinued and a write-back operation is carried out to change a threshold voltage of the memory cell in the reversed direction. In addition, the configuration also allows the number of charge-pump stages in an internal power-supply configuration to be changed in accordance with the level of a power-supply voltage so as to make the write-back operation correctly executable. As a result, no memory cells are put in deplete state even in the event of a power-supply cutoff in the course of a write or erase operation.

Abstract: The development of Flash memory technology over the past decade has been one of the driving forces behind the tremendous growth in digital consumer applications, such as digital cameras, handheld music players and mobile phones. NAND Flash has been leading the way from 16Mb in 1994 to 4Gb today. This paper discusses the impact of continuous advances in NAND Flash technology on consumer applications and also reviews technical challenges to the further scaling of NAND and NOR Flash memories, while considering the possibility of other nonvolatile memory technologies for high density nonvolatile data storage beyond 2010.

Abstract: A method of manufacturing a non-volatile flash memory device, including setting a first number of bits stored per cell for at least one first cell less than a second number of bits stored per cell for at least one second cell such that the setting permanently fixes the first number and the second number prior to shipping the device for use Preferably the setting is based on predicted reliabilities of the cells Preferably, the predicted reliability of the first cells is less than the predicted reliability of the second cells Preferably, the setting is based on respective locations within the device of the first cells and the second cells Preferably, the setting is based on respective word lines connecting to the first cells and the second cells

Abstract: Non-volatile memory devices and arrays are described that utilize reverse mode non-volatile memory cells that have band engineered gate-stacks and nano-crystal charge trapping in EEPROM and block erasable memory devices, such as Flash memory devices. Embodiments of the present invention allow a reverse mode gate-insulator stack memory cell that utilizes the control gate for programming and erasure through a band engineered crested tunnel barrier. Charge retention is enhanced by utilization of high work function nano-crystals in a non-conductive trapping layer and a high K dielectric charge blocking layer. The band-gap engineered gate-stack with symmetric or asymmetric crested barrier tunnel layers of the non-volatile memory cells of embodiments of the present invention allow for low voltage tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention.

Abstract: A data management apparatus and method used in a system using one or more flash memories, which can deal with defective blocks in each of the flash memories using different methods depending on how the system manages data stored in each of the flash memories. The data management apparatus includes a device driver, which controls the operation of one or more flash memories, and a controller, which transfers data stored in a defective block of one of the flash memories to a predetermined block in the flash memory.

Abstract: A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.

Abstract: Data remanence is the residual physical representation of data that has been erased or overwritten. In non-volatile programmable devices, such as UV EPROM, EEPROM or Flash, bits are stored as charge in the floating gate of a transistor. After each erase operation, some of this charge remains. Security protection in microcontrollers and smartcards with EEPROM/Flash memories is based on the assumption that information from the memory disappears completely after erasing. While microcontroller manufacturers successfully hardened already their designs against a range of attacks, they still have a common problem with data remanence in floating-gate transistors. Even after an erase operation, the transistor does not return fully to its initial state, thereby allowing the attacker to distinguish between previously programmed and not programmed transistors, and thus restore information from erased memory. The research in this direction is summarised here and it is shown how much information can be extracted from some microcontrollers after their memory has been ‘erased'.