Abstract: A memory apparatus for vehicle information is provided in which the image data of the vehicle's condition in a traffic accident, a traffic offense, a drive condition from the occurrence of an accident to the vehicle's stop after the accident, and a sensor data are memorized and held in a flash memory repeatedly. The memory apparatus enables an analysis of an accident with high precision upon the reproduction of the data of the vehicle's condition, and can be used to provide evidence relating to a traffic offense. The image signals from a CCD camera 1, a RAM 12 for memorizing the sensor's information from a vehicle speed sensor 3, a steering angle sensor 4, a brake pressure sensor 5, and an acceleration sensor 6, and a flash memory 13 for permanently memorizing the signals of the RAM 12, are controlled through a CPU 11. The record information of the RAM 12 is transferred to the flash memory 13 based on the operation of a collision sensor 2 to memorize and hold the information. Moreover, the signal of the flash memory 116 is converted into a video signal to output the information during a reproduction.

Abstract: A non-volatile flash store memory system for storing persistent data with low overhead. The flash store comprises an active flash memory sector and one or more non-active backup sectors. Each memory sector includes a header to indicate the status of the sector and multiple data records, each with their own headers. The data records are organized by key identifiers in combination with offset values to create a linked-list file structure. New records in the active sector can be sequentially added, while existing records can be marked as deleted if it is desired to remove them. Extra memory space can be recaptured by performing a compacting sequence, in which the active records are copied from the active sector to a backup sector, while skipping those records that are marked as deleted. Upon successful completion of the copying process the backup sector becomes the new active sector, and the former active sector is marked as inactive. The compacting sequence is performed so that there is always a valid copy of each data record at all times, and no data will be lost in the event of a power failure or other similar anomaly.

Abstract: Nonvolatile memory cell and process in which a control gate or a thick dielectric film is used as a mask in the formation of a floating gate and also as a step in the formation and alignment of a select gate. The floating gate is relatively thin and has a side wall with a rounded curvature which, in some embodiments, serves as a tunneling window for electrons migrating to the select gate during erase operations. In other embodiments, the gate oxide beneath the floating gate is relatively thin, and the electrons tunnel through the gate oxide to the source region in the substrate below.

Abstract: A multi-level non-volatile memory includes one or more arrays of memory cells including storage cells and dummy cells. The memory observes or measures write operations that write dummy values to the dummy cells and from the observations or measurements selects parameters such as programming voltages or the duration of program cycles. The selection of parameters optimizes write precision within the available access time of a high bandwidth memory. Accessing dummy cells also allows the memory to reach a steady state before writing or reading of data begins. In particular, multiple pipelines sequentially start write operations, and writing of data begins when an equilibrium number of pipelines are performing write operations. Similarly, multiple read operation start before the reading of data for actual use. The stabilization is particularly critical when the pipelines share a power source.

Abstract: Proposes a new way of managing flash memory space for flash memory-specific file systems based on a log-structured file system. Flash memory has attractive features such as non-volatility and fast I/O speed, but it also suffers from an inability to update in place, and limited usage cycles. These drawbacks require many changes to conventional storage (file) management techniques. Our focus is on lowering the cleaning cost and evenly utilizing flash memory cells while maintaining a balance between these two often-conflicting goals. The cleaning efficiency is enhanced by dynamically separating cold data and non-cold data. The second goal, cycle leveling, is achieved to the degree where the maximum difference between erase cycles is below the error range of the hardware. Simulation results show that the proposed method has a significant benefit over naive methods: a maximum of 35% reduction in the cleaning cost with evenly-spread writes across segments.

Abstract: An interfacing system facilitating user-friendly connectivity in a selected operating mode between a host computer system and a flash memory card. The interfacing system includes an interface device and a flash memory card. The interfacing system features significantly expanded operating mode detection capability within the flash memory card and marked reduction in the incorrect detection of the operating mode. The interface device includes a first end for coupling to the host computer and a second end for coupling to the flash memory card, while supporting communication in the selected operating mode which is also supported by the host computer system. The flash memory card utilizes a fifty pin connection to interface with the host computer system through the interface device. The fifty pin connection of the flash memory card can be used with different interface devices in a variety of configurations such as a universal serial mode, PCMCIA mode, and ATA IDE mode. Each of these modes of operation require different protocols. Upon initialization with the interface device, the flash memory card automatically detects the selected operating mode of the interface device and configures itself to operate with the selected operating mode. The operating mode detection is accomplished by sensing unencoded signals and encoded signals. The encoded signals are encoded with a finite set of predetermined codes. Each predetermined code uniquely identifies a particular operating mode.

Abstract: From the Publisher: This book introduces embedded systems to C and C++ programmers. Topics include testing memory devices, writing and erasing flash memory, verifying nonvolatile memory contents, controlling on-chip peripherals, device driver design and implementation, optimizing embedded code for size and speed, and making the most of C++ without a performance penalty.

Abstract: A software loading system for a funds processing station for recording and reconciling financial data, the software loading system comprises a resident memory containing an initial software code to be executed by the controller; and a flash card (2540) having a flash card memory (2536) containing a second software code. The flash card (2540) is adapted to be removably electrically coupled to the funds processing machine (2010). The resident memory is adapted to erase the initial software code and store the second software code in response to the flash card being electrically coupled to the funds processing machine (2010). The resident memory is adapted to retain the second software code in response to the flash memory card (2540) being thereafter removed from the funds processing machine (2010).

Abstract: A NAND type flash memory device has a reference bit line and a reference page buffer to control sensing time during program and erase verification operations. Each reference memory cell in the reference bit line is pre-programmed with a reference bit. A set initiation signal triggers detection and latching of the reference bit by the reference page buffer. When the reference bit is latched, an output of the reference page buffer is used as a set signal to trigger the program and erase verification operations of corresponding memory cells.

Abstract: A novel cell conditioning mechanism is employed to equalize charge discharge characteristics of flash memory cells. A variable conditioning signal removes charge from "fast" bits in the array, and leaves other cells relatively unaffected so that the fast bits are adjusted to have threshold voltages closer to those of the other cells in an array. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.

Abstract: An improved flash memory system includes a flash array, internal buffer, and internal controller. When data is written from a source block to a destination block, the improved flash memory system temporarily holds this data inside the internal buffer within the flash memory system to save the overhead of sequentially transferring the data out of the flash system and then sequentially returning the data back to the system. Alternatively, the data can be read and concurrently programmed onto the destination block without being written into an internal latch. In use, this improved flash memory system simply transfers the data to be rewritten from the flash array either directly or to the internal buffer. This improved flash memory system locates a new address within this same flash array.

Abstract: An electrically-programmable read-only-memory (EPROM) and a flash memory cell having source-side injection are formed with a gate dielectric material, and a pair of gates that are both formed on the gate dielectric material. The gate dielectric material has substantially more electron traps than hole traps so that the gate dielectric material is capable of having a negative potential which is sufficient to inhibit the formation of a conductive channel during a read operation.

Abstract: A storage device (10) has a flash memory (11), a controller (16), and a second ROM (15). In the flash memory (11), a data key is stored, which is a key specific to each storage device (10). In the second ROM (15), a system key is stored, which is an encrypting key common to storage devices (10). The controller (16), to write data, encrypts the data with the data and system keys and writes the encrypted data in the flash memory (11); and to read data, decrypts the data with the data and system keys to output the decrypted data. The data key may be encrypted with the system key. In this case, to write data, the controller (16) may decrypt the data key with the system key, and encrypt data with the decrypted key; and to read data, the controller may decrypt the data key with the system key, and decrypt the encrypted data with the decrypted data key.

Abstract: A method and apparatus for increasing the amount of memory available to a host device that utilizes flash memory are disclosed. In a preferred embodiment, a flash card comprising flash memory and a transmitter for transmitting data via wireless communication is utilized within a host device. Such flash card may store data in its flash memory, and may transmit data from the flash card to an extended storage device via wireless communication. In a preferred embodiment, such wireless communication is radio frequency (RF). Data transfer from the flash card to an extended storage device may be initiated by a mechanism on the flash card or on the host device. In a preferred embodiment, the flash card further comprises a receiver for receiving wireless signals. In such an embodiment, an extended storage device may initiate a data transfer by transmitting the appropriate signals to the flash card. In a preferred embodiment, an extended storage device may comprise a transmitter for further transmitting the data to another storage device(s). Such transmitter may be a more powerful transmitter than provided in the flash card, such that the extended storage device may transmit data to a more remote location. Advantageously, in a preferred embodiment an extended storage device may be a less expensive form of storage than flash memory.

Abstract: The object of the present invention is to reduce the dispersion of the threshold after writing while maintaining the high speed nature of a write system in a nonvolatile semiconductor memory such as a flash memory of channel hot electron write type The feature of this invention is to provide a memory with a write current detection type write circuit and a sense amplifier for read, and to switch, for verification at the time of write, between verification by the write current type write circuit and verification of normal read mode which uses the sense amplifier for read In other words, when a cell threshold of write level is designated as a first threshold and a specified threshold level lower than the first threshold is designated as a second threshold, write operation by the write current detection type write circuit is performed at the beginning of write mode, and stops the write operation when the current flowing between the drain and the source of the memory cell falls to below or equal to the reference current corresponding to the second threshold Thereafter, the write operation is performed by repeating the write operation and verification operation using the sense amplifier until the cell threshold reaches the first threshold

Abstract: A flash memory device includes an array of core cell blocks and page buffers with supporting input/output circuitry. The flash memory device, in addition, contains a mechanism for precharging the bitline line of each page buffer prior to the sensing/evaluation cycle of a particular memory element in each core cell block. The precharging mechanism increases the speed of response in retrieving information from each core cell block because the bitline line is charged to a predetermined voltage prior to accessing the bitline. The precharging mechanism includes a first transistor connected between a power supply and the bitline that is operational during the precharge cycle and causes the bitline to charge to the predetermined voltage. The precharging mechanism also includes a second transistor connected between a latch disposed in the page buffer and ground. The second transistor grounds the latch prior to the start of the evaluation cycle.

Abstract: The source end of a NAND string in a scalable, lower voltage flash memory device is biased during a memory read operation to prevent problems associated with punchthrough. Due to the biasing, the channel length of the floating gate transistors in the flash memory device can be shortened, and the pass voltage employed during the memory read operation can be lowered.

Abstract: A flash memory device of the present invention increases a speed of reading data. The conventional art has a problem of losing data due to data collision when increasing the data reading speed by making an operation of an external clock signal fast. However, the flash memory device of the present invention has an advantage of preventing the data loss even in a fast data reading operation by using a temporary buffer and an output control signal for outputting data in the data reading operation.

Abstract: A computer system includes a Flash or other nonvolatile memory. A program(s) to coordinate data transfers is loaded into a volatile system memory to transfer data from an external device to the Flash memory. The data transferred from the external device to the Flash memory can be transferred to a previously unused portion of the Flash memory, or alternatively can overwrite a previously used portion of the Flash memory. According to one aspect of the invention, the data is transferred from the external device to the volatile system memory and then from the volatile system memory to the Flash memory, allowing additional verification steps to help insure that the data is transferred intact. According to another aspect of the invention, data is copied from the external device to the Flash memory on a portion by portion basis, leaving a set of critical portions to be transferred last.

Abstract: Program disturb in a Flash storage array is reduced by applying a voltage level that depends on the threshold level of a previously programmed cell to the word-line of that cell during programming of subsequent cells on the same bit-line. By applying higher voltages to word-lines containing unselected programmed memory cells with higher threshold voltages, program disturb due to these higher threshold cells is reduced.

Abstract: This short paper describes a technique for the measurement of the electric near field at the package surface of microprocessors and other VLSI devices. The technique uses precision stepper motors for highly accurate placement of an electric field probe at the surface of the device to be measured. Structural resolution across the device is on the order of 400-600 /spl mu/m. Typical scans accumulate 10000 data points across a variable scan area, which can be defined by device package dimensions or by the die dimensions. Characterizing a device involves a repeated series of surface scans at harmonics of the fundamental clock frequency. This paper describes the electric near field at the surface of a multichip module (MCM) composed of a processor, a flash memory, and application specific integrated circuit (ASIC). The MCM was measured while in operation in the actual circuit application.

Abstract: A memory system (10) comprising a non-volatile memory (18) having memory locations (38), and a controller (16) for writing data structures to and reading data structures from the memory. The system (10) is architecturally configured so that the locations (38) can be written to individually but are erasable only in blocks. The controller (16) forms one or more erasable units (39) which are each subdivided into cells (50) each consisting of a group of locations (38). The controller (16) writes data structures to and reads structures from each cell (50) on a per cell basis. The system (10) may comprise a controller (16) embedded in a FLASH memory card. Alternatively, the controller (16) may be embedded in, or implemented in, a host system such as a Personal Computer (PC).

Abstract: A content addressable memory (CAM) includes non-volatile CAM cells that are in an array similar to a conventional Flash memory array. In the CAM, each word line connects to control gates of Flash memory cells in a row, each bit line connects to drains of Flash memory cells in a column, and each match line is a source line coupled to sources of Flash memory cells in a row. A 2-T CAM cell includes a pair of non-volatile devices coupled to the same word line and match line. Each non-volatile device can be a floating-gate transistor, a Flash memory cell, or a shared-floating-gate (SFG) device. An erase of a CAM word applies erase voltages to the word and match lines associated with the word. The erase does not depend on the bit line voltages. Accordingly, the CAM array can simultaneously perform a search and an erase. With SFG devices, the CAM array can also simultaneously perform a search and a program operation. A CAM buffer stores words to be written in the array and can also conducts a search during an erase so that the CAM can perform back-to-back write and search operations without waiting for completion of an erase operation. A dual CAM cell includes a combination of two CAM elements, each CAM cells being, for example, a known or new 2-T CAM cell. The first element stores a data bit of a CAM word. A second element is programmed to either represent the data bit or a “don't care” state. A search without masking uses the first element in each dual CAM cell, and a search with masking uses some or all of the second elements depending on a mask selection register. To change masking for a particular CAM word, the first element is read, and the second element is reprogrammed according to the value read and the desired masking.

Abstract: A new, negative V/sub th/ cell architecture is proposed where both the erased and the programmed state have negative V/sub th/. This architecture realizes highly scalable, excellently noise-immune, and highly reliable NAND flash memories. The program disturbance that limits the scaling of a local oxidation of silicon (LOCOS) width in a conventional NAND-type cell is drastically reduced. As a result, the scaling limit of the LOCOS width decreases from 0.56 to 0.45 /spl mu/m, which leads to 20% isolation width reduction. The proposed cell is essential for the future scaled shallow trench isolated cells because improved program disturb characteristics can be obtained irrespective of the process technology or feature size. New circuit techniques, such as a PMOS drive column latch and a V/sub cc/-bit-line shield sensing method are also utilized to realize the proposed cell operation. By using these novel circuit technologies, array noise, such as a source-line noise and an inter bit line capacitive coupling noise, are eliminated. Consequently, the V/sub th/ fluctuation due to array noise is reduced from 0.7 to 0.1 V, and the V/sub th/ distribution width decreases from 1.2 to 0.6 V. In addition to the smaller cell size and the high noise immunity, the proposed cell improves device reliability. The read disturb time increases by more than three orders of magnitude, and a highly reliable operation can be realized.

Abstract: An input circuit for a flash memory device is disclosed. The input circuit includes an input for receiving a voltage signal from an external source representing a digital logic signal. The input circuit further includes a pull up circuit which is coupled with the input and pulls the input to a high logic level when the input is not connected to any external source.

Abstract: A hand-held battery powered device for transferring data between one or more flash memory modules and a mass storage device. The device includes one or more slots to accept a flash memory module into a housing which includes fixed or removable mass storage device and logic circuitry disposed within the housing for transferring data between the flash memory module and mass storage device. Ports are disclosed for transferring data from the resident mass storage device to the user's computer.

Abstract: Leakage detection for cells in a flash memory device. According to one embodiment of the present invention a method includes reading a flash cell in a read cycle in a flash memory device to generate a read signal, generating several reference signals, comparing the read signal with each of the reference signals in the read cycle, generating a data signal based on the comparison to indicate data stored in the flash cell, and generating a refresh signal based on the comparison to request a refresh of the flash cell if the flash cell is leaky. According to another embodiment of the present invention a flash memory device includes a number of flash cells, a read circuit to generate a read signal in a read cycle of the flash memory device by reading a selected one of the flash cells, a reference circuit to generate a plurality of reference signals, and a comparing circuit to compare the read signal with each of the reference signals in the read cycle to generate a data signal indicating data stored in the selected flash cell and to generate a refresh signal if the selected flash cell is leaky.

Abstract: A BIST circuit built in a LSI device incorporating a LSI memory such as a DRAM, a SRAM, a Flash memory, and the like has a repair code generator/register ( 7 ) and a selector ( 6 ) or a self repair circuit ( 8 ). The repair code generator/register ( 7 ) generates a repair code regarding information of a redundancy memory cell to be used instead of a faulty memory cell when a comparator ( 3 ) indicates that a memory cell array ( 51 ) includes the faulty memory cell. The selector ( 6 ) selectively outputs data stored in the GO/NG register ( 4 ) and the repair code generator/register ( 7 ). The self repair circuit ( 8 ) repairs the faulty memory cell based on the repair code.