Abstract: Electric field coupling between floating gates of a high density flash EEPROM cell array has been found to produce errors in reading the states of the cells, particularly when being operated with more than two storage states per cell. The effect of this coupling is overcome by placing a conductive shield or insulating material with a low dielectric constant between adjacent floating gates, and/or by compensating for the coupling when reading the states of the cells.

Abstract: A method for organizing a flash memory in which the size of the memory portion for reading or writing data, such as a block, differs from the size of the smallest portion for erasing, such as a unit. The method of the present invention is particularly useful for page-mode devices exemplified by the NAND and AND technologies, in order to enable these devices to be reorganized when no more unwritten physical units are available.

Abstract: A memory system including an array of flash EEPROM cells arranged in blocks of cells that are erasable together, with individual cells storing more than one bit of data as a result of operating the individual cells with more than two detectable threshold ranges or states. Any portion of the array in which data is not stored can be used as a write cache, where individual ones of the cells store a single bit of data by operating with only two detectable threshold ranges. Data coming into the memory is initially written in available blocks in two states since writing in more than two states takes significantly more time. At a later time, in the background, the cached data is read, compressed and written back into fewer blocks of the memory in multi-state for longer term storage at a reduced cost.

Abstract: A flash memory chip that can be switched into four different read modes is described. In asynchronous flash mode, the flash memory is read as a standard flash memory. In synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock period. The data stored at the specified addresses are output sequentially during subsequent clock periods. In asynchronous DRAM mode, the flash memory emulates DRAM. In synchronous DRAM mode, the flash memory emulates synchronous DRAM.

Abstract: A World Wide Web browser software is implemented in a processing system housed in a set-top box connected to a television and communicating over a wide-area network with one or more servers. The browser software allows a user to navigate using a remote control through World-Wide Web pages in which a number of hypertext anchors are displayed on the television. User inputs are entered from a remote input device using an infrared (IR) link. The processing system includes a read-only memory (ROM) and a flash memory. The mask ROM and the flash memory are assigned adjacent memory spaces in the memory map of the processing system. Browser software and configuration data are stored in the flash memory. Other software and configuration data are stored in a mask ROM. The browser is upgraded or reconfigured by downloading to the box replacement software or data transmitted from a server over the network and then writing the replacement software or data into the flash memory. A mechanism is provided to temporarily maintain power to the processing system in the event power to the box is lost during downloading. The mechanism allows the writing of a current block to be completed. An indication of the current block is maintained while power is absent so that downloading can be resumed once power is restored from the last block that was written.

Abstract: A flash-memory device has been fabricated and demonstrated at room temperature by coupling a self-aligned, sub-50-nm quantum dot to the channel of a transistor on a silicon-on-insulator (SOI) substrate. Large threshold voltage shifts of up to 0.75 V are obtained for small erase/write voltages (13 V) at room temperature. At 90 K, evidence of single electron storage is observed. The small size of this device is attractive for achieving high packing densities, while the relatively large output current (100 nA-/spl mu/A's), low off-state current (10 pA), and simple fabrication, requiring only minor variations in standard processing, make it suitable for integration with current silicon memory and logic technology.

Abstract: A flash memory chip that can be switched into four different read modes is described. In the first read mode, asynchronous flash mode, the flash memory is read as a standard flash memory where the reading of the contents of a first address must be completed before a second address to be read can be specified. In the second read mode, synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock tick. Then, the contents stored at the addresses specified for the burst are output sequentially during subsequent clock ticks in the order in which the addresses were provided. Alternately, if a single address is provided to the flash chip when it is in the synchronous mode, the subsequent addresses for the burst will be generated within the flash chip and the data burst will then be provided as output from the flash chip. In the third read mode, asynchronous DRAM mode, the row and column addresses are strobed into the flash memory using strobe signals. The flash memory then converts the row and column addresses internally into a single address and provides as output the data stored at that single address. The flash memory does not need an extended precharge period or to be refreshed, but can be controlled by a standard DRAM controller. In the fourth read mode, synchronous DRAM mode, the flash memory emulates a synchronous DRAM.

Abstract: A system in which a plurality of wireless interface devices, each containing one or more flash memory devices, are interfaced to a server which may be connected in either a wireless or wired LAN by way of a radio link. The system in accordance with the present invention, enables the flash or other type of memory devices in the plurality of wireless interface devices interfaced to the server to be updated over a radio link.

Abstract: A flash-memory system is expandable. Rather than directly connecting individual flash-memory chips to a controller, flash buffer chips are used. Each flash buffer chip can connect to four banks of flash-memory chips. Chip enables for individual chips in a bank are generated from an address sent to the flash buffer chips. Two flash-specific DMA controllers are provided, each with four DMA state machines for controlling the four banks of flash-memory chips attached to a flash buffer chip. This allows for four-way interleaving. Two flash buses connect the two DMA controllers to flash buffer chips. The flash bus has a narrow byte-wide interface to send command, address, and data bytes from the DMA controller to the flash buffer chips. These command, address, and data bytes are then passed through the flash buffer chip to the flash-memory chips. Two additional command signals on the flash bus are used to select and control the flash buffer chips. Busy signals from all flash-memory chips in a bank are connected together, and the four busy signals from the four banks are time-multiplexed to a single common busy line for the flash bus. The four DMA state machines each monitor one period of the busy line, allowing four flash operations to be monitored at a time, even though only one data transfer can occur across the flash bus.

Abstract: A system is described which stores data intended for defective memory cells in a row of a memory array in an overhead location of the memory row. The data is stored in the overhead packet during a write operation, and is read from the overhead packet during a read operation. A defect location table for the row of the memory array is provided to identify when a defective memory cell is address;ed for either a read or write access operation. During a write operation, the correct data is stripped from incoming data for storing into the overhead packet. During a read operation, the correct data is inserted into an output data stream from the overhead packet. Data written to defective cells can be either a custom setting, a default setting, or the original data. Shift registers are described for holding good data during either a read or write operation. The number of shift registers used is determined by the number of states stored in a memory cell. The shift registers use a marker for alignment ofdata bits in a data stream.

Abstract: This work presents recent results on Secondary Electron flash memory, and contrasts this approach to standard for scaled, low power mass storage applications.

Abstract: An architecture for microcontroller with embedded flash memory is provided. The microcontroller allows the reprogramming of data into the embedded flash memory of the microcontroller to be performed on-board without having to dismount the entire IC package of the microcontroller from the circuit board and then use a dedicated writer to perform the write operation. The reprogramming operation can be initiated either by an external reprogramming-enable signal or an internal reprogramming-enable signal. When either of these two signals is generated, it causes an OR gate to output a high-voltage logic signal to a multiplexer to thereby cause the multiplexer to select a ROM unit for connection to the microprocessor unit. This allows the microprocessor unit to execute a reprogramming control routine stored in the ROM unit. The flash memory unit further stores a reprogramming detection/initialization routine which checks whether a flash reprogramming request signal is issued from the main-unit interface. With this microcontroller architecture, the reprogramming of data into the embedded flash memory can be performed on-board without having to laboriously dismount the microcontroller from the circuit board. The reprogramming operation is therefore quite easy and quick to perform, thus more cost-effective than the prior art.

Abstract: A flash-memory system adds system-overhead bytes to each page of data stored in flash memory chips. The overhead bytes store system information such as address pointers for bad-block replacement and write counters used for wear-leveling. The overhead bytes also contain an error-correction (ECC) code when stored in the flash-memory chips. A DRAM cache stores the pages of data as enlarged pages with the overhead bytes, even though the enlarged pages are not aligned to a power of 2. When an enlarged page is read out of a flash-memory chip, its ECC code is immediately checked and the ECC code in the overhead bytes is replaced with a syndrome code and stored in the DRAM cache. A local processor for the flash-memory system then reads the syndrome code in the overhead bytes and repairs any error using repair information in the syndrome. The overhead bytes are stripped off when pages are transferred from the DRAM cache to a host. The host can be notified early by an intermediate interrupt after a programmable number of pages have been read. This improves performance since the host does not have to wait for an entire block of pages to be read.

Abstract: A semiconductor nonvolatile memory device enabling high speed, high precision data programming and have a large disturb margin, that is, a NAND type flash memory wherein the programming operation is performed by repeating a programming operation a plurality of times through a verify read operation, where the programming word line voltages VPP1 to VPPk and an intermediate prohibit voltage VM1 to Vmk are set to values which are incremented along with an increase of the number k of programming and where the voltage increments of the intermediate prohibit voltage for each increase of the number of programming is set to half of the voltage increments of the programming word line voltage for each increase of the number of programming. Due to this, high speed, high precision data programming becomes possible and further the degradation of the disturb margin can be eliminated.

Abstract: In a digital system having a host, a controller device and at least one flash memory integrated circuit, a method and apparatus for storing location identification information regarding blocks of information within at least one of the flash memory integrated circuits wherein at least two buffers within the at least one of the flash memory integrated circuits are designated as primary and secondary buffers for storing the identification information in the primary buffer until the primary buffer is effectively full and storing additional identification information in the secondary buffer until it is effectively full, swapping buffer designation so that the primary buffer becomes the secondary buffer and the secondary buffer becomes the primary buffer, erasing the effectively-full buffer for re-use and in this manner, continuously swapping storage of identification information between the two buffers.

Abstract: A semiconductor storage device connectable to a host information processing apparatus having a flash memory section that stores data in sectors and wherein the flash memory section includes an address management table that stores information about the relation between logical sector numbers for data management in a host information processing apparatus and physical sector numbers for data management in the flash memory section. The flash memory section also includes a table state map that stores information about the physical locations at which the sector number information in the address management tables is stored. The semiconductor storage device also includes a flash memory control circuit for controlling data write and data read processing for the flash memory section. The control circuit refers to the table state map when the host information processing apparatus requests data write or data read to identify the physical location at which the corresponding address relation information is stored and converts the logical sector number received from the host information processing apparatus into a physical sector number based on the value stored at the identified location in the address management tables.

Abstract: Single-event upset was investigated in high-density flash memories from two different manufacturers. Many types of functional abnormalities can be introduced in these devices by heavy-ions because of their complex internal architecture. Changes in the stored memory contents sometimes occurred, even when devices were irradiated in a read mode with the internal charge pump inactive. For one device technology, unusually high currents were observed during post-irradiation cycling that were high enough to cause catastrophic failure.

Abstract: An improved system and method for FLASH BIOS upgrades which is particularly useful in network hubs. Each hub or node which is equipped with a FLASH memory is also equipped with a validation system, which ensures that a received FLASH upgrade is authorized and uncorrupted. Each set of instructions to be flashed is marked both with a vendor authorization digital signature and also a system administrator authorization digital signature, and BOTH digital signatures must be recognized by the validation system before the FLASH memory will be upgraded. Because digital signatures are used for security purposes, flash upgrades can be performed from any location on the network, and are not limited to an administrative node.

Abstract: This paper describes a flash memory server (FMS) for personal communication devices and embedded home information systems, such as set-top boxes and Internet phones. Flash memory is small, lightweight, shock-resistant, nonvolatile, and requires little power. Writing to flash memory segments requires erasing the segment in advance. However, erase operations are slow and power-wasting and usually decrease system performance. The number of erase cycles is also limited. To reduce the number of erase operations needed and to evenly wear the flash memory, a new flash memory management scheme has been designed. A new cleaning policy is also proposed to reduce cleaning overhead. Performance evaluations show that erase operations can be reduced by 55%.

Abstract: We describe circuit techniques for a Flash memory which operates with a V/sub DD/ of 1.5 V. For the interface between the peripheral circuits and the memory core circuits, two types of level shifter circuits are proposed which convert a V/sub DD/ level signal into the high voltage signals needed for high performance. In order to improve the read performance at a low V/sub DD/, a new self-bias bitline voltage sensing scheme is described. This circuit greatly reduces the delay's dependence on bitline capacitance and achieves 19 ns reduction of the sense delay at low voltages. Multilevel storage sensing with this circuit is also discussed.

Abstract: A record/playback device for use with a removable, interchangeable, flash memory recording medium which enables noise dampened recording of voice data and CD quality stereo recording of music data. The device includes a port for receiving a flash memory module which can record data according to industry standard formats to enable the transfer of data to and from personal computers through swapping of flash memory media. Alternative forms of data input and output also include implementation of a barcode reader and an infra-red transceiver for the transfer of data to and from the device.

Abstract: An array of MOS memory cells having functionally symmetrical drain and source regions may be programmed and/or erased using low voltage, e.g., less than about 7V. In a NAND-type array, UV-erasure increases threshold voltage Vt to erase memory cell contents, and low voltage-low current hot-hole injection ("HHI") decreases Vt to program the memory cells. For NOR-type arrays, HHI decreases Vt to erase memory cell contents and channel-hot-electron ("CHE") injection increases Vt to program cell contents. Erase and program potentials are low (<7V), enabling arrays to be readily fabricated on a common IC with low voltage circuits. Because HHI strongly converges Vt, the memory cells may store more than two data values, which increases cell storage density. Cell symmetry permits swapping drain for source before cell endurance becomes too troublesome, which swapping can substantially increase the endurance lifetime for an array. Arrays may be used as flash memory, as EPROM replacement, or as one-time-programmable memory.

Abstract: A compact on-chip error correcting circuit (ECC) for low cost flash memories has been developed. The total increase in chip area is 2%, including all cells, sense amplifiers, logic, and wiring associated with the ECC. The proposed on-chip ECC, employing 10 check bits for 512 data bits, has been implemented on an experimental 64M-bit NAND flash memory. The cumulative sector error rate has been improved from 10/sup -4/ to 10/sup -10/. By transferring read data from the sense amplifiers to the ECC twice, 522-Byte temporary buffers, which are required for the conventional ECC and occupy a large part of the ECC area, have been eliminated. As a result, the area for the circuit has been drastically reduced by a factor of 25. The proposed on-chip ECC has been optimized in consideration of balance between the reliability improvement and the cell area overhead. The power increase has been suppressed to less than 1 mA.

Abstract: A flash memory cell. The cell includes a transistor with a floating gate that is formed from a number of crystals of semiconductor material. The crystals are disposed in the gate oxide of the transistor. The size of the crystals and their distance from a surface of a semiconductor layer of the transistor are chosen such that the crystals can trap a single electron by hot electron injection. Each trapped electron causes a measurable change in the drain current of the transistor. Thus, multiple data bits can be stored and retrieved by counting the changes in the drain current.

Abstract: A flash memory using the alternating word-line voltage pulses is experimentally studied. Relations between pulse count and the threshold voltages of the cell are obtained. An automatic threshold voltage convergence was confirmed by the relation, and the threshold voltage is successfully controlled by the word-line pulse voltage. An application to a multi-level flash memory is proposed.

Abstract: This paper discusses a novel flash memory featuring a selfaligned split gate structure with sub-0.lpm sidewall gate length, source side injection for programming, band-to-band tunneling for erasing, and an oxide/nitride/oxide (ONO) stack for charge storage. The bitcell is suitable for low voltage (1.8V) and high density (cell size 1.35 km2 using 0.4 Fm technology) applications.

Abstract: A program drain voltage pump is provided that employs multiple pumping sections that are adaptively controlled to provide a pumped drain voltage (VD) that rises smoothly and rapidly to an optimum VD level for programming EPROM or flash memory cells and maintains VD at the optimum level with minimal ripple. The pumping sections are configured to pump a common VD node that is coupled to the drains of the EPROM or flash memory cells. Each pumping section is driven by a clock signal whose pulses are out of phase with the clock signals driving the other pumping sections. All of the clock signals have roughly the same frequency. Due to the staggered clocks, each pump is activated during a different respective time period, which smooths out VD. Additionally, to provide an even faster and smoother pumped VD than with multiphase clocking alone, an embedded controller is provided that adaptively adjusts the frequency and slew rate of the various clock pulses throughout the pumping operation, which alters the amount by which VD is raised for a given clock pulse.

Abstract: A multilevel non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In alternative embodiment, a refresh process includes reprogramming the threshold voltage into an allowed state or in the case of a flash memory, reading a sector of the memory, saving data from the sector in a buffer, erasing the sector, and rewriting the data from the buffer back in the sector. Refresh process for the non-volatile memory can be perform in response to detecting a threshold voltage in a forbidden zone, as part of a power-up procedure for the memory, or periodically with a period on the order of days, weeks, or months.

Abstract: The present invention provides a structure and method of manufacturing split gate MONOS multi-level logic memory device. The memory device has a poly stacked gate transistor 20A in series with a MONOS transistor 24A. The device has a novel operation to achieve multi-level memory storage (e.g., 4 voltage states). The method begins by forming a tunnel oxide layer 30 on the surface of a semiconductor substrate 10. The substrate having a stacked gate channel area 20 and a MONOS channel area 24 in the active regions. A poly floating gate electrode 32 is formed over the stacked gate channel region 20. A ONO layer having a memory nitride layer is formed over the floating gate 32 and the tunnel oxide layer over the MONOS channel region 24. A control gate electrode 44 is formed over the ONO layer 41 spanning across the poly floating gate electrode 32 and the MONOS channel region 24. Source/drain regions 50 51 are formed in the substrate. A poly flash transistor 20A and a MONOS flash transistor 24A combine to form the 4 level logic memory cell of the invention.