Abstract: A flash memory with multilevel cell significantly reduces the memory per-bit cost. A 32 Mb multilevel-cell (MLC) flash memory storing two bits of data per cell achieves 32 Mb memory storage capacity using 16 M flash memory cells. This 32 Mb flash memory on a 0.6 /spl mu/m process has a 2.0/spl times/1.8 /spl mu/m/sup 2/ flash cell. In MLC operation, the logical flash memory cell achieves two bits per cell using four possible states, defined by four flash cell threshold voltage ranges. The relationship between the threshold voltage ranges stored in the flash memory cell and the corresponding logic levels is shown in this paper, which also shows a plot of the four threshold voltage distributions, each with a separation range.

Abstract: A device employing a redundant array of solid state memory devices is presented, whereby RAID technology architecture is uniquely combined with solid state memory devices. The devices comprises a plurality of circuit boards assemblies mounted within a housing, preferably a housing which fits into a standard 51/4 inch computer drive bay or a rack mount housing. The circuit board assemblies are electrically connected to solid state memory devices, for example, flash memory PCMCIA cards. A data path controller circuit provides the interface between a host system and the flash memory cards.

Abstract: A flash memory system having a controller and a flash memory device for providing BIOS, operating system and user storage capabilities is provided. According to exemplary embodiments of the present invention, flash memory systems can be designed as integrated circuit packages which are pin compatible with conventional ROM BIOS chips so that existing systems can be readily upgraded without extensive modifications.

Abstract: A file system created in a flash EEPROM memory array for an embedded system having a plurality of blocks of flash memory cells, each block being divided into identical-sized areas capable of being addressed, the file system including a data structure positioned at a predetermined one of the areas on each block of a flash EEPROM memory array, the data structure storing a logical identification of data stored in each of the areas, the logical identifications of data being stored sequentially in the physical order of the areas on the block, a controller implemented process for searching the predetermined ones of the areas on each block to detect a logical identification of data, and means for accessing the physical area associated with any logical identification of data which is detected.

Abstract: A peripheral device control system includes a single flash memory having a changeable portion for storing firmware for controlling the peripheral device and a preprogrammed portion containing control code. When it is desired to modify the changeable firmware, the control code is read from the flash memory to a storage area in the using system and is used to control the loading of the modified firmware in the flash memory.

Abstract: A semiconductor disk device 2A comprises a flash memory 8A having a plurality of blocks and a CPU 4 for converting a logical sector address into a physical-logical block number and its offset value, for searching for a block and a data memory area in the flash memory 8A based on the physical-logical block number and offset value, and for reading the content of the data memory area when no chain data is stored in an update data chain information memory area. The block comprises a physical-logical block memory area, a plurality of data memory areas for storing data, data status flag memory areas, one disposed corresponding to each of the data memory areas, for storing a data status flag that indicates whether the data memory area stores data, and update data chain information memory areas, one disposed corresponding to each of the data memory areas, for storing chain information indicative of the destination of data. The usual address conversion table for memory management is dispensed with, and accordingly, the data areas are expanded. Another embodiment has a block address conversion table linked to the CPU 4.

Abstract: A wireless interface device is adapted to be interfaced with a host computer by way of a radio link. A wireless interface device includes one or more flash memory devices that are adapted to be updated by the host computer over the radio link.

Abstract: A flash memory controlling system is disclosed which includes: a flash memory for storing therein data; a check code generating circuit for generating a data error check code; a storage circuit for storing therein the error check code generated by the check code generating circuit; and a control circuit for implementing a process sequence for data read-out or data write-in on the flash memory while storing in the storage circuit the error check code generated by the check code generating circuit for data stored into the flash memory.

Abstract: A portable automotive diagnostic tool (30) for receiving information from an automotive computer of a vehicle. The portable automotive diagnostic tool (30) is battery powered. The portable automotive diagnostic tool (30) comprises a microcontroller (31), a display (32), a keypad (33), a flash memory (34), a SRAM (35), a battery backup circuit (36), a ROM (37), a UART (38), and a port (39). Automotive codes for configuring the portable automotive diagnostic tool (30) are stored in flash memory (34). The automotive codes are compressed to increase storage to the flash memory (34). The flash memory (34) is non-volatile and retains the automotive codes when power is removed. The automotive codes are updated by writing new automotive codes to the flash memory (34). Information or data received from an automotive computer is stored in SRAM (35). The battery backup circuit (36) powers the SRAM (35) to maintain the information to be taken to a different location when the power is turned off.

Abstract: A flash memory system including an array of flash memory cells and at least one programmed reference cell and at least one erased reference cell disposed in a common integrated circuit. Memory array read operations are carried out by reading the two reference cells and the target cell of the memory array. The two reference cells produce a programmed reference output and an erased reference output which are averaged to provide a reference value to be compared with the read output of the target cell. In that the reference value is derived by on-chip programmed and erased cells, the reference value will automatically adapt to changes in the fabrication process, temperature, operating voltages and the like. Preferably, the reference cell outputs are also utilized to adaptively control the programming and erasing of the memory array cells so as to control the erased and programmed threshold voltages of the array cells.

Abstract: The new portable computing and telecommunications market requires high performance, low power, high density electrically reprogrammable non-volatile memories. Memories integrated with information handling circuits on SOI wafers can offer significant advantages for high speed computation, better isolation, lower leakage, better noise immunity, and excellent CMOS latch-up margin. A NOR Virtual Ground (NVG) flash memory cell fabricated on an SOI wafer is considered. The fabrication process for NVG on SOI can be unchanged if the silicon thickness of the SOI wafer is properly chosen and doped, such that the N+ bit-line (Source/Drain) touches the oxide layer. One important feature of cells on SOI is that it is difficult to ground the p-body of cell and it will be left floating during all memory operations. Therefore, it is important to study the effect of the floating body on channel-hot-electron (CHE) programming and Fowler-Nordheim (F-N) channel erase used in NVG flash memory.

Abstract: This paper proposes a new bit-by-bit verify circuit for application in NAND flash memories. The Sense Amplifier (S/A) employed confers two benefits: flexible power supply voltage (ex. 3 V or 5 V) operation with a high noise immunity and an intelligent page copy function. The benefits are very useful to the flash memory card or system and accelerate the replacement of magnetic memories by flash memories. The S/A has been successfully implemented in the commercial version of the 32 Mbit NAND-EEPROM, in which the S/A is newly introduced in comparison with the prototype version.

Abstract: A battery operable ambulatory and non-ambulatory patient monitoring system that includes storage to a solid-state flash memory which storage is controlled in a manner to optimize power consumption, to have a variable sampling rate, to have up to 24 input data channels and to provide as an option loss-less data compression in the processor.

Abstract: A novel electron injection scheme for flash memory is proposed, where band-to-band tunneling induced hot electrons (BBHE) are employed in a P-channel cell. This proposed method ensures the realization of high program efficiency, high scalability and hot-hole-injection-free operation. We also demonstrate an application of the method to DINOR (DIvided bit-line NOR) program operation. An ultra-high-speed programming of 60 nsec/Byte can be achieved with a leakage current less than 1 mA by utilizing 512 Byte parallel programming. This new DINOR flash memory is shown to be the most promising for the realization of a low-voltage, high-performance and high-reliability flash memory of 64 Mbits and beyond.

Abstract: Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell (401) having n states, where n is a power of two, is determined by selectively comparing the threshold voltage Vt of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator (460 and 470) is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.

Abstract: A method of quickly aborting an automated program or erase sequence on a nonvolatile memory array in which each operation of the sequence is performed by a write state machine. During each operation of the program or erase sequence, the state of an abort signal is detected to determine whether or not the sequence should be aborted. If the abort signal is in a second state, the sequence continues to the next operation. If the abort signal is in a first state, the write state machine aborts the sequence and the nonvolatile memory array is placed in a read-only mode. The nonvolatile memory array is then available for user access.

Abstract: A method for programming an array of memory cells wherein each cell may be placed in more than two states. The method comprises the steps of 1) selecting a plurality of different programming voltage levels wherein each programming voltage level is associated with a corresponding one of a plurality of states, and 2) applying a plurality of programming pulses to selected subsets of the array of memory cells, wherein each programming pulse has one of the programming voltage levels and one of a corresponding plurality of pulse widths such that each of the memory cells of a corresponding one of the selected subsets are programmed directly to a corresponding one of the plurality of states by a corresponding programming pulse.

Abstract: Addresses for a plurality of consecutive logic blocks are managed by assigning the addresses to their corresponding addresses for physical blocks of a plurality of flash memory devices such that the addresses for the plurality of continuous logic blocks are respectively distributed into the plurality of flash memory devices. When block erase commands are inputted from the outside, chip enable signals are respectively transmitted to at least two of the flash memory devices in which physical blocks to be erased exist, in such a manner that a period in which at least two flash memory devices simultaneously perform block erase operations, exists.

Abstract: A flash memory and its data refresh method, where data read out in program verify mode and erase verify mode from read address are compared in each address (ST110), and data of a memory cell corresponding to inconsistent data are rewritten (ST112). Or adding values of data read out in the program verify mode and the erase verify mode are compared in each block (ST137) and a defective block is retrieved and data in each address are compared in the defective block (ST160), and data of a memory cell corresponding to inconsistent data are rewritten (ST162). Thereby, defective data can be retrieved and corrected.

Abstract: This paper presents an analytical model for the description of the programming operation in split-gate source-side injection flash memory devices. From a dual-gate MOS model and from device simulations, it is found that the lateral field is almost independent of the floating-gate voltage which focuses the description of the gate current during programming on the physics of the Si-SiO/sub 2/ barrier lowering effect. The traditional Lucky Electron Model is used to accurately describe the gate current and, therefrom, the programming characteristic is calculated analytically with a minor approximation. The validity and the usefulness of the model for device design purposes is demonstrated by comparing the results to experimental data obtained from flash EEPROM cells fabricated in a 1.2 /spl mu/m and a 0.7 /spl mu/m technology, respectively. >

Abstract: A computer system includes a flash memory device for storing BIOS code. The BIOS code is stored in an unprotected area of the flash memory. A boot block, stored in a protected area of the flash memory, is used for rebooting the computer system in the event that the flash memory device becomes corrupted. During normal operation, the BIOS code is updated using a radio link. If the BIOS is corrupted while being updated, a recovery routine stored in the boot block is executed. The recovery routine permits the corrupted BIOS to be reprogrammed using a serial interface instead of the radio link.

Abstract: A controller circuit that controls the transfer of a computer operating system from a host computer into a hand-held computer system through the parallel port without the need of intervention from the microprocessor. The operating system is loaded into flash memory devices located in the hand-held computer. The protocol used for the transfer is the IEEE 1284 bi-directional parallel port specification. To begin the transfer of data, the host computer performs a negotiation according to the 1284 standard with the hand-held computer. After the host computer has determined that the hand-held computer is 1284 compliant, it embeds two flash command bytes to indicate the type of command to be performed, selects the desired banks of flash memory, and selects the block in the flash memory. The commands that are performed include a write, a read array, a block erase, a read ID, a read status register, a clear status register, and a parallel port disable command. The controller circuit performs handshaking functions through the parallel port with the host computer, and it seizes control of the system data bus when a transfer is desired.

Abstract: Multiple logic levels can be programmed into a single EPROM or FLASH memory cell by applying one of a corresponding number of programming voltages to the control gate of a memory cell that is biased so that the source-to-substrate junction becomes forward-biased and the drain-to-substrate junction becomes reverse-biased. During programming, the bias conditions form substrate hot electrons which, in addition to the channel hot electrons, accumulate on the floating gate. By utilizing the substrate hot electrons, a much lower control gate voltage can be utilized during programming. More importantly, however, once the channel hot electrons cease to exist, the substrate hot electrons and holes converge to a stable charge that is related to the control gate voltage used during programming and the programmed threshold voltage of the cell.

Abstract: In a computer-driven device, a start-up mode after reset is provided whereby boot-up instructions are by default always accepted directly from an external source. The device may comprise a gate array (GA) which is connected directly via a serial port to a receiving or input device, to receive program code for transfer directly as instructions to a microprocessor-type central processing unit. The central processing unit is part of a computer controlled device containing a microprocessor, memory (a RAM), and typically a bulk erase flash memory device, the flash memory device being unprogrammed when the computer controlled device is fabricated originally. When the computer controlled device first powers up, a special mode of operation ensues in which the gate array directly monitor bits received via the serial port from the input device and shifts them into a local register from which bytes or words are loaded directly into the CPU as instructions. A boot sequence is thereby accepted in this manner to load random access memory of the free-running CPU which thereafter can control transfer of additional executable code or load a permanent boot sequence into bulk erase (nonvolatile) flash memory. The invention can be incorporated into a wireless modem/packet terminal node controller. The input device may be a coupling to an external computer system, typically a serial input.

Abstract: We have developed a novel NOR-type flash memory technology named Dual String NOR (DuSNOR). In the DuSNOR cell array, two adjacent cell strings share a source line and up to 128 cell transistors can be attached to a string. This makes the cell size of DuSNOR smaller than NAND, without sacrificing the advantages of the NOR-type cell. Both the program and erase operations utilize the Fowler-Nordheim tunneling. DuSNOR cells with a cell size of 1.60 /spl mu/m/sup 2/ was fabricated using 0.5 /spl mu/m design rules. It was found that the DuSNOR cell has a fast operating speed, reduced overprogram and disturb problems, and excellent endurance characteristics. DuSNOR is a promising technology for high density, high speed, and random-access flash memories with a small cell size, excellent device characteristics and simplicity in the fabrication process.

Abstract: An electronic voting system (20) includes a central judges station (22) having a detachable flash memory cartridge (42) for use in storing election data. The data contents of the memory cartridge (42) are shadowed by identical storage in a separate flash memory module (74). The memory cartridge (42) is retained by a password-protected solenoid lock mechanism (44) to preserve the integrity of election results. The station (22) is networked to a plurality of voting booths (24 and 26) that provide ballot selections to the judges' station (22).

Abstract: According to a time required for programing operation, respective chips of flash memories are divided into a first group and a second group of chips requiring a time longer than the first group for the programing operation, and a postburn-in test, a high temperature test, and a low temperature test are carried out to a plurality of chips belonging to the first group simultaneously, and to a plurality of chips belonging to the second group simultaneously.

Abstract: This paper describes the design and implementation of a memory management method, Link-Fit, which allows transparent hardware data compression to be incorporated in a flash-memory based disk. Link-Fit is compared with the standard method for flash-memory management, which writes sequentially and uses copying compaction for storage reclamation. Flash-memory is different from DRAM on three accounts, it is non-volatile, it must be explicitly erased on a block basis before it can be rewritten, and it has a relatively low write performance. Data compression can improve the effective capacity, and hence the $/MB ratio by a factor of two. Likewise the write performance can be improved by a factor of two, since only half the amount of data must be written to the non-volatile store. As a result of using data compression the memory manager must handle variable sized blocks efficiently, in terms of both time overheads and storage utilisation.

Abstract: First and second flash memory cells or transistors, operating in the linear region of operation, are provided with different threshold values by providing different charges on their respective floating gates. The first of the pair of flash memory transistors is "over-erased" until it has a negative threshold voltage so that the first flash memory transistor is rendered permanently conducting when its control gate and source are at V ss . Circuitry is provided for connecting the first and second flash memory transistors in parallel circuits in which equal current values are generated in an equilibrium condition. Circuitry for sensing a voltage in each of the parallel circuits is provided to determine any imbalance in current values and provide an output voltage which may be used as an reference value when the currents are in equilibrium. Circuitry is provided for sensing variations in the output voltage to vary the current through one of the flash memory transistors to bring the currents into equilibrium when the output voltage varies from the reference value provided at equilibrium. The control gate of the first (over-erased) flash memory transistor is connected to the system ground, V ss to further increase the stability of the reference voltage generator.