Abstract: Reliability issues for flash electrically erasable programmable read-only memories are reviewed. The reliability of both the source-erase type (ETOX) flash memory and the NAND structure EEPROM are discussed. Disturbs during programming, write/erase endurance, charge loss of both devices are reviewed, and the reliability of the tunnel oxide and the interpoly dielectric are described. It is shown that bipolarity F-N programming/erase, which is used in the NAND EEPROM, improves the charge to breakdown and decreases the stress-induced leakage current. >

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A flash memory system includes a user interface and array controller The user interface receives the user command issued by the processor and has the ability to queue a plurality of commands for execution The user interface further functions as an arbiter to control the priority of commands to be executed The array controller performs the operations on the flash array such as program and erase The array controller consists of a general purpose processor with program memory which is programmable by the user The program memory stores one or more algorithms that can be executed by the array controller The algorithm is selected according to the command received at the user interface The algorithms can be customized simply by programming the program memory The system further provides an interrupt mechanism which enables the flash memory system to perform a context switch of a higher priority command with the lower priority, but currently executing, command

Abstract: A method of increasing the data throughput of a memory device including a page buffer. Data throughput is increased by pipelining write operations such that one plane of the page buffer is being used to program the memory array of the device while the other plane of the page buffer is being loaded with data to be used in the next program operation. The first write operation is set up by loading a first block of data in to the first plane of the page buffer. In the following clock cycle, the first operation begins by commanding the memory device to program the memory array with the first block of data stored in the first plane. The second write operation is setup immediately following the first command to program. The second write operation is setup by loading a second block of data into the second plane of the page buffer. Loading of the second plane occurs while the memory array is being programmed from the first plane. The second write operation begins by commanding the array controller to program the flash memory array with the second block of data stored in the second plane.

Abstract: A flash memory device having a plurality of flash array blocks and a block status register circuit containing a block status register for storing a block status for each flash array block. A flash array controller circuit in the flash memory device performs program or erase operations on the flash array blocks, and maintains the block status in each block status register. An interface circuit in the flash memory device enables read access of the block status registers over a bus.

Abstract: A plurality of consecutive sector numbers are assigned to a plurality of flash EEPROM chips in a semiconductor memory system. The results of assigning the consecutive sector numbers are held in an address conversion table as address conversion information. Thus, the flash EEPROM chips are simultaneously accessed when a host CPU designates the consecutive sector numbers for the same track. The access speed of the semiconductor memory system can therefore be increased when the system is controlled by the existing disk access method in which the sectors to be accessed sequentially are assigned to the same track. The semiconductor memory system can thereby be used efficiently in place of a data storage disk.

Abstract: A method and device for selectively enabling and disabling write access to flash blocks in a flash memory device. A lock command locks and unlocks a flash block in a flash array containing a plurality of flash blocks. A block data row decoder selects a block data area of the flash block, and a block status row decoder selects a block status area of the flash block. A lock bit in the block status area is programmed to a first logic state if the lock command specifies a lock flash block operation, or to a second logic state if the lock command specifies a release flash block operation. If a write protect input, read from the write protect pin of the flash memory device, indicates that a write lock is enabled and if a block enabled status bit in a block status register corresponding to the block indicates that the block has the write lock, then the lock bit is read and stored into the block enabled status bit in the block status register corresponding to the block. The write protect input is read again from the write protect pin and if the write protect input indicates that the write lock is enabled, and if the block enabled status bit in the block status register corresponding to the block, as updated, indicates that the block has the write lock, then an error is signaled.

Abstract: The operation of the flash memory, which has matured over the last five years from a novelty product, is described. Both dual and single supply voltage devices are considered. Flash memory cycling, data reliability, program/erase algorithms, and blocking are discussed. Three approaches to flash memories are examined. The uses of these devices and some new architectures are considered. >

Abstract: Word line stress is used to narrow the distribution of threshold voltages after an erase of an array of memory cells. One embodiment of the invention provides a method for erasing an array including a standard erase technique followed by extra erase pulses to create a margin between threshold voltages of the cells and the erase verify level, then applying word line stress to narrow the distribution of threshold voltages. Another embodiment in addition includes verifying that all of the memory cells are still erased after applying word line stress and if any of the memory cells were over-stressed and are not erased, repeating the method but using less word line stress. The erase methods according to embodiments of the present invention can be implemented by an external CPU which executes an erase program or by circuitry embedded in an EEPROM.

Abstract: An N-channel SNOS or SONOS type memory array (100) has programmable memory states with a negative, depletion mode threshold lower in magnitude than the supply voltage VCC when erased and a positive threshold when programmed. During reading, the supply voltage VCC is applied to the drain (16), while a positive voltage VR less than VCC-Vds,sat is applied to the source (14), where Vds,sat is the saturation voltage of the device. A reference voltage may also be applied to the substrate (11) during a read operation. Selected devices have VR applied to the gate (12), while inhibited devices have ground or the substrate potential VSS applied to the gate (12).

Abstract: From the Publisher: Since its introduction as a commercial product, flash memory has been adopted into a very broad range of applications, ranging from proprietary embedded systems to personal computers. Finally, a book has been written on this innovative technology, helping you master techniques for integrating it into your designs. Here's where you'll get all of your flash-related questions answered: How does it work? What are the different types, and how do they differ? What is a flash file system? What special hardware and software do flash cards require? Learn detailed flash memory design principles. Become an expert in implementing and optimizing systems containing flash memory, whether used for embedded firmware or secondary mass storage. Starting with the fundamentals, this book explains the read, write and erase mechanisms of the flash cell, including the software algorithms for the various flash memory technologies. Flash memory voltage generation and power consumption is another very important, and often overlooked, topic covered here. This book sorts out the essential elements of a flash file system and provides an analysis of the different approaches in use today. Learn how to implement the flash memory control signals and interpret AC timing waveforms. Discover what it takes to integrate flash cards into your PCMCIA or ExCA compatible systems, both from a hardware and a software standpoint (including a detailed explanation of Socket Services). Designing with Flash Memory is the flash "bible". If your job requires you to be up to date on the newest technology, you need this book now!

Abstract: A reference scheme for verifying the erasing and programming in an electrically erasable and electrically programmable read-only memory fabricated on a silicon substrate which employs a plurality of memory cells, each of which contains a floating gate. The reference scheme employs trimmable single cell reference devices for both the erase verify and program verify operations. The threshold voltages of the reference cells are trimmed to a level below (in the case of the erase verify reference cell) or above (in the case of the program verify reference cell) which all memory cells in the array will be considered in a particular program state (i.e., erased or programmed). In the case of the read reference device, a double-cell read referencing device combining the erase and program verify reference cells is described. Although, the double-cell referencing device is preferred, a trimmable read reference device is also taught.

Abstract: Disclosed is a circuit and method for utilizing FLASH devices as nonvolatile storage elements. Information is modified by adding a new block of data at another location in the memory rather than writing over the outdated information. An address pointer locates the latest information for each data file.

Abstract: A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a contiguous extended memory space accessible over a host bus. The page buffer circuit also maps the plane A and the plane B as a control store for a flash array controller of the flash memory device.

Abstract: Erase control circuitry for erasing a flash memory array. The erase control circuitry resides on the same substrate as the flash memory array, along with a command state machine. The command state machine recognizes and externally generated erase command applied to the terminals and generates an active erase control signal, to which the erase control circuitry responds. The erase control circuitry includes precondition pulse application circuitry, erase pulse application circuitry and erase verification circuitry. The precondition pulse application circuitry preconditions the array by programming each bit in the flash memory to a threshold voltage level representative of a programmed state. The erase pulse application circuitry applies a single erase pulse at a time to the flash memory array to erase the flash array by bringing the threshold voltage level of each cell in the array to a level representative of an erased state. The erase verification circuitry verifies the erasure of the flash memory array on a byte by byte basis. If the byte currently being verified has been erased; the erase verification circuitry brings a match signal to an active level. The erase control circuitry determines whether additional erase pulses should be applied to the flash array based upon the match signal and the number of erase pulses previously applied to the flash array described is program control circuitry and methods of programming and erasing a flash memory array in response to two step command sequences.

Abstract: A system includes a portable remote terminal for communicating with other terminal devices and an external unit for inputting information. The portable remote terminal has a connector for connecting the portable remote terminal to the external unit, a flash memory for storing information used in the portable remote terminal, a debugging tool area provided with the flash memory, the debugging tool area storing a program in accordance with which the information stored in the flash memory is rewritten, and a controller for rewriting the information stored in the flash memory so as to be information, input by the external unit and supplied from the external unit via the connector, the rewriting being in accordance with the program stored in the debugging tool area of the flash memory.

Abstract: An integrated circuit (1) comprises a functional module (2) such as a FLASH memory with automatic program and erase circuits, test circuitry (3) coupled with the functional module which executes a test of the functional module and generates status information as a result of the test, and non-volatile status write circuitry coupled with the test circuitry on the chip. A circuitry in the non-volatile status write circuitry is responsive to the test of the functional circuitry to write the status information to the non-volatile memory. A port (5) is provided on the integrated circuit coupled to the non-volatile memory (4) through which the status information stored in the non-volatile memory is accessible in a test read mode to external devices. In a FLASH EPROM embodiment, the IC includes an array of FLASH EPROM memory cells and a port through which data in the array is accessible by external devices. A test set of FLASH EPROM memory cells is provided in the array. Program and erase circuitry, coupled to the array, has a test mode to exercise the program and erase circuitry to generate status information indicating results of the test and test read mode to read out the status information. Non-volatile status write circuitry is coupled to the program and erase circuitry and the test set, and writes the status information to the test set. The program and erase circuits include retry counts with programmable thresholds for reducing the test times of the devices.

Abstract: A new 3-D sidewall flash EPROM cell has been implemented in a novel memory array. The sidewall cell is a single-transistor stacked gate cell built on the sidewalls of a silicon pillar. The gates surround the pillar and current flows vertically from top to bottom of the pillar. The cell size approaches the square of the minimum pitch and is less than 40% of that of the conventional NOR-type structure. The cell and array architecture promise to be highly scalable. >

Abstract: In a memory device in a bare chip state which is determined as fail by over erasing during a test at a wafer level, information indicating the presence of an over-erased memory cell is stored in a nonvolatile and readable manner into an identification memory circuit, and then memory cells in a memory cell array are restored to an erase state of an electrically neutral state by irradiation with an energy beam such as ultraviolet rays. A chip erased by the energy beam such as ultraviolet rays is assembled as an OTPROM (one-time programmable read only memory) and tested. At that time, a writing/erasing control circuit for controlling data writing into and data erasing in the memory cells is brought into an operation inhibited state in accordance with the information stored in the memory circuit. It is possible to reduce the rate at which fail products are produced by use of a flash memory which is determined as fail because of the presence of an over-erased memory cell as a one-time programmable memory device.

Abstract: A method of operating a flash memory semiconductor device is provided. The semiconductor device formed on a substrate lightly is doped with a dopant. A source region and a drain region are formed in the substrate on the surface thereof. A dielectric layer is deposited upon the substrate. A floating gate electrode is formed on the dielectric layer proximate to at least the edges of the source region and the drain region. Additional dielectric material is deposited upon the surface of the floating gate electrode, and a gate electrode is deposited upon the surface of the additional dielectric material.

Abstract: A method of enabling access to a test mode of a semiconductor memory in response to user commands. The method enables test mode access only when a number of "keys" are presented in the proper sequence via the memory device pins. During the first phase of the unlocking process, an array controller determines whether the correct confirmation codes were input via the address and data pins. If they were, the array controller proceeds to the second phase of the unlocking process. During the second phase voltage levels on selected control pins are checked for a transition to a first voltage level. If the control pins transition as required, the array controller proceeds to the third phase. During the third phase, the array controller waits a limited time for receipt of a second test mode enable command. The second test mode enable command must be followed by correct confirmation codes. If the third phase is successfully completed, the array controller writes to a test mode enable access register. As a result, an enable test mode signal becomes active, which allows the user interlace to respond to subsequently issued test mode commands. Also described is a method of eliminating access to the test mode of the semiconductor memory device, which includes a nonvolatile instruction memory.

Abstract: A flash memory cell includes the usual thermal oxide layer deposited above the substrate including the source and the drain. On the thermal oxide layer, a silicon rich oxide layer is formed. Above the silicon rich oxide layer a gate structure is formed of layer of polysilicon separated by an intermediate dielectric layer. The lower polysilicon layer commences as an initial portion of the layer of small grain size followed by either amorphous or large grain size material.

Abstract: An electrically erasable non-volatile semiconductor memory device has a memory cell array, a first erase unit, a second erase unit, and an operation mode establish unit. The erasing operation of the second erase unit is independently carried out of the erasing operation of the first erase unit. When a first operation mode is established by the operation mode establish unit, the second erase unit is inactivated, and the erasing operation of the memory cell array is only carried out by the first erase unit. On the other hand, when a second operation mode is established by the operation mode establish unit, the erasing operation of the first erase unit for a part of the memory cell array is disable, and the second erase unit is activated and the erasing operation for the part of the memory cell array is carried out by the second erase unit. Therefore, the change between a boot block type flash memory and normal type flash memory can be realized only by changing an establish value of the operation mode establish unit. Consequently, when developing both boot block type flash memory and normal type flash memory, these two types of flash memories can be obtained by using the same chip or by carrying out only minimum changes, so that the developing processes can be greatly decreased.

Abstract: Hot-hole injection into the opposite channel of silicon-on-insulator (SOI) MOSFETs under hot-electron stress is reported. Sequential front/back-channel hot-electron stressing results in successive hot-electron/-hole injection, causing the threshold voltage to increase and decrease accordingly. This ability to inject hot holes into the opposite gate oxide can be used as an additional tool for studying the degradation mechanisms. Furthermore, it can be explored for possible use in designing SOI flash memory cells with back-channel-based erasing schemes. >

Abstract: The process for controlling a flash memory according to the invention includes the operations consisting in (a) dividing the storage region of a flash memory into several sectors, where each sector includes a logic address segment (10) intended for storing a logic address of the sector, an erase management segment (11) intended for stashing information which indicates at least whether the sector can be erased, and a data segment (12) intended for stashing data, and (b) in accessing an arbitrary sector of the flash memory by specifying the logic address of the arbitrary sector. The invention also relates to an apparatus for controlling a flash memory which uses this process.

Abstract: A memory array configuration and a decoder circuits for the DINOR flash memory have been described. The hierarchical row decoder and the compact source line driver realize 1K byte sector erasure without increasing the decoder area. The decoder pitch has been relaxed to one driver per two word lines. Narrow threshold voltage distribution has been realized by the bit-by-bit programming control and the low threshold voltage detection circuit, which achieves high speed random access time at low Vcc. A 4 Mb test device was fabricated in a 0.5 /spl mu/m CMOS triple well process and a typical access time of 90 ns was obtained at Vcc of 3 V.

Abstract: A semiconductor integrated circuit device comprises a central processing unit (CPU), a first external terminal (EA0-EA16), and an electrically erasable and programmable nonvolatile flash memory (FMRY), wherein the semiconductor integrated circuit has a first operation mode in which the flash memory receives an address signal from the central processing unit executing a control program to erase and write data from and into the flash memory, and wherein the semiconductor integrated circuit has a second operation mode in which the flash memory receives an address signal on the external terminal to write data supplied from the outside of the semiconductor integrated circuit device into the flash memory.

Abstract: We proposed previously [1] a novel flash memory cell structure named DINOR (Divided bit-line NOR ) utilizing Fowler-Nordheim erase/write operation, which has realized low power dissipation and high performance with low cost. In this paper, a new application of this DINOR operation ( F-N erase/write ) to a virtual ground array flash memory is described. By using a novel asymmetrical offset source/drain structure, small cell size of 1.0/spl mu/m/sup 2/ based on 0.5/spl mu/m CMOS process will be realized and which makes it possible to realize high speed 3V only 64M bit flash memory.