Abstract: A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.

Abstract: A circuit for testing the data failure rate of a flash memory array comprising apparatus for writing a test pattern to a memory array; and apparatus positioned in a data path prior to the interface between the memory array and circuitry external to the memory array for detecting differences in data read from the memory array and the test pattern written to the memory array, the last mentioned apparatus including apparatus for reading data from the memory array, apparatus for comparing the value of data read from the memory array with the value of data written to the array in the test pattern, and apparatus for storing a indication that a comparison has produced a result indicating a failure to compare.

Abstract: A nonvolatile semiconductor memory device particularly relates to an EEPROM having NAND-structured cells, and an optimizing programming method thereof. The device includes a memory cell array arranged as matrix having NAND cells formed by a plurality of serially-connected memory cells each of which is formed by stacking a charge storage layer and a control gate on a semiconductor substrate, and enables electrical erasing by the mutual exchange of a charge between the charge storage layer and the substrate, a data latch circuit, a high voltage supply circuit, a current source circuit, a program checking circuit, and a program status detecting circuit. The programming state is optimized while being unaffected by the variance of process parameters, over-programming is prevented by the use of a verifying potential, and the performance of the chip is enhanced by automatically optimizing the programming with a chip's internal verification function. External control is not required, which enhances performance of the overall system. Also, a page buffer of an existing flash memory having the page mode function is employed, which is applicable to the currently used products.

Abstract: A personal computer uses a flash memory equipped with a main block storing a boot block and a basic input/output system as its BIOS-ROM. An address translation circuit, after power-on reset, supplies addresses output by a central processing unit to the BIOS-ROM as they are to thereby allow access to the boot block storing a far jump instruction. After system startup, the address translation circuit inverts a predetermined bit of each address output by the CPU to thereby allowing access to the BIOS. To refresh the contents of the BIOS-ROM, the CPU transfers a BIOS stored on a floppy disk to the main block of the BIOS-ROM.

Abstract: A novel flash cell structure named DINOR (DIvided bit-line NOR) whose bit-line is divided into main and sub bit-line, having a unit consisting of one select transistor and 8 stacked gate cells, is proposed. By combining this cell structure and gate-biased FN erase/write operation, we have succeeded in making a cell that has little drain disturb, high over erasure tolerance, low power dissipation, possibility of 3 volt operation, high data transfer rate, and small erase unit, without losing fast random access. All of the disturbs and single-cell endurance characteristics proved to be acceptable. Moreover, using several self-align processes, 2.88 mu m/sup 2/ cell size based on 0.5 mu m CMOS process is realized, which is a 20% cell area reduction compared with the conventional NOR cell. >

Abstract: A 5-V-only 16-Mb CMOS flash memory with sector erase mode is described. An optimized memory cell with diffusion self-aligned drain structure and channel erase are keys to achieving 5-V-only operation. By adopting this erase method and row decoders to apply negative bias, 512-word sector erase can be realized. The auto chip erase time of 4 s has been achieved by adopting 64-b simultaneous operation and improved erase sequence. The cell size is 1.7 mu m*2.0 mu m and the chip size is 6.3 mm*18.5 mm using 0.6- mu m double-layer metal triple-well CMOS technology. >

Abstract: A flash memory comprises a cell matrix, in which rewritable nonvolatile memory cells (591ij) are arranged at intersections between a plurality of word lines (WLi) and a plurality of bit lines (BLi), and also comprises row decoders (587) for applying specified voltage selectively to the word lines (WLi) during writing or reading. The flash memory further comprises: switch circuits (590i) that are located between the cell matrix and the row decoder (587) in association with the word lines, and that enter a cutoff state when the word lines are set to negative voltage and enter a conducting state on any other occasion; negative-voltage bias circuits (592) whose negative-voltage output terminals (554) are connected to the word lines (WLi), and that apply the voltage output of a negative power supply to the word lines in response to a clock pulse (CLK) ; and clock pulse control circuits (593, 594) for causing the clock pulse (CLK) to be supplied to the negative-voltage bias circuit when it is detected during erasing that the word lines (WLi) are selected. The word lines (WLi) are divided into a plurality of groups and the clock pulse control circuits (593, 594) are operable to cause the clock pulse (CLK) to be supplied to each of the negative-voltage bias circuits connected to the selected word lines in a group when any word lines in the group are selected.

Abstract: Circuitry for independently controlling the erasure of a flash memory including redundant rows for replacing shorted rows within the memory array is described. An erase command fires a sequencer circuit, which schedules the controllers that execute the tasks of an erase event. By nesting the control of erase events, the sequencer circuit allows easy modification of erase events. The sequencer circuit fires a precondition controller upon receipt of an erase command. The precondition controller then manages the preconditioning of the memory array, including memory cells within shorted rows. The precondition controller does so by disabling the replacement of shorted rows with redundant rows. During preconditioning each memory cell is programmed to a logic 0, before the memory cell is erased to a logic 1, to prevent the overerasure of memory cells during subsequent erasure. Afterward, the sequencer fires the erase controller. The erase control circuit then manages erasure. The circuitry also includes a postcondition controller and a program controller.

Abstract: The present invention relates to a flash EEPROM cell using polysilicon-to-polysilicon hot electron emission to erase the memory contents of the cell. Exemplary embodiments include a side gate, a control gate, a floating gate and source and drain regions. Appropriate biasing of these gates and source and drain regions controls the electron population of the floating gate. The memory cells may be of either the double polysilicon or triple polysilicon variety. Peripheral transistors are formed from a last formed polysilicon layer to avoid degrading the peripheral transistors.

Abstract: A semiconductor flash memory cell which includes a P type substrate with an N type well formed therein followed by a P type well formed within the N well. An N type drain is formed in the P well as is an N type source, with the drain and source being spaced apart so as to create a channel region therebetween. A floating gate is disposed over only a part of the channel and a first segment of a control gate is disposed over the remainder of the channel. A second segment of the control gate is disposed over the floating gate. The arrangement of the floating and control gate functions to eliminate adverse effects of over erase. In addition, the well-within-a-well structure enables biasing voltages to be applied during erase which forces electrons removed from the floating gate to enter the channel region, rather than the drain region thereby increasing the program/erase cycle endurance of the cell.

Abstract: A novel erasing scheme has been developed to suppress the distribution of the erased cell threshold voltage (erased-V). The new 2-step erasing scheme consists of two steps of the cell gate bias conditions, that is to apply 1) negative high voltage on the control gate to erase the cell data, and successive 2) positive high voltage to inject a few electrons from the substrate back to the floating gate. The suppressing effect of the erased-V distribution was also confirmed using a 16 Kbit flash memory cell array, the erased-V/sub /distribution drastically decreases from 2.0 V by the conventional erasing scheme to 0.9 V using the 2-step erasing scheme. >

Abstract: Flash memory (12) is added to a printer and fonts and macros received at connector (14) are stored under operator control. All data received is first processed under by the printer data processor controller (8) using dynamic memory (10). Printers which respond to more than one language store the downloaded information before termination of a language mode erases the DRAM.

Abstract: A method of reducing the degradation effects associated with avalanche injection or tunnelling of hot-electrons in a field-effect semiconductor device is disclosed. The method of the present invention includes covering the active regions of the semiconductor device with a protective titanium barrier layer which is deposited directly underneath the ordinary metalization layers used for connecting the devices to bit and word lines within an array. Inclusion of the titanium barrier layer in a flash memory device results in a substantial improvement in the erasetime push-out and reduces excess charge loss normally associated with hot-electron devices.

Abstract: A flash memory card is described which has a ready/busy mask register. First and second flash memories of the flash memory card have respective first and second outputs indicating ready or busy status for the first and second memories. The ready/busy mask register contains mask data. Logic circuitry performs (1) a first logical operation between a first output and a first mask datum to produce a first masked output, (2) a second logical operation between a second output and a second mask datum to produce a second masked output, and (3) a third logical operation between the first masked output and the second masked output to produce a flash memory card ready/busy output. The flash memory card has circuitry for providing a ready output signal that indicates a first (in time) transition from a busy mode to a ready mode by either the first flash memory or the second flash memory of the flash memory card.

Abstract: A method for determining the capacitive coupling coefficients of flash erasable programmable read only memories (EPROMs) is introduced. This technique relies on the Fowler-Nordheim erase measurements and source/drain junction leakage characteristics of the device to extract the control gate, source, and drain coupling coefficients. An advantage offered by this method is its use of an actual flash EPROM cell without requiring additional test structures. >

Abstract: A flash memory is operable using a single power supply voltage. In this flash memory, an internal booster circuit boosts the supply voltage to generate a write voltage higher than the supply voltage. A row decoder is connected to word lines, which are connected to memory cells. Upon reception of an address signal, the row decoder selects a word line specified by this address signal. A row-line clamp circuit, which is connected to the internal booster circuit and the word lines, supplies the write voltage to a word line selected at the time of data writing, and drops the write voltage and supplies it to the selected word line at the time of write verify.

Abstract: A technique for determining the sign and the effective density of the trapped oxide charge near the junction transition region, based on the measurement of the gate-induced drain leakage (GIDL) current, is used to investigate the hot-carrier effects resulting from the erase operation and bit-line stress in flash EPROM devices. While the trapped oxide charge depends on the stress conditions, it has been found that a significant amount of hole trapping is likely when a sufficiently large potential difference exists between the gate and junction for either an abrupt or graded junction. >

Abstract: The authors describe a decoding scheme and erase sequence for a 5-V-only sector-erasable flash memory. A source line decoder eliminates the erase disturb problem and lowers the power consumption. The maximum switching voltage is reduced to 10 V, which makes possible a tight word line pitch for a 64-Mb flash memory. Narrow threshold voltage distribution of erased memory cells is obtained by programming after erase. >

Abstract: A device for achieving optimum erasure of the memory cells of a NAND type flash EEPROM. A memory string comprises a bit line, word lines and cell transistors with the gates respectively connected to the word lines and the channels cascaded between the bit line and ground voltage. A high voltage supplying device is connected between the bit line and the memory string for generating a first high voltage. A bit line selection transistor has the channel connected between the high voltage supplying device and the memory string and the gate connected to a bit line selection signal. In a first erasing operation, an erasing voltage applying device applies a first voltage to the gate of the bit line selection transistor and an erasing voltage to the gates of the cell transistors. In a second erasing operation, it applies a second voltage to the gate of selected transistor of the cell transistors, a third voltage to the gates of one group of the cell transistors between the selected cell transistor and the ground voltage, a second high voltage to the gates of another group of the cell transistors between the bit line and selected cell transistor and the gate of the bit line selection transistor, and the first high voltage to the drain of the selected cell transistor.

Abstract: PURPOSE:To provide the system which does not require battery backup for holding a program executing state during a power source is turned off CONSTITUTION:When the power supply switch of a switch circuit 6 is turned off, a state storage device 1 saves the program executing state (such as the contents of all the registers in a CPU 5, the contents of an I/O register in a peripheral device 4, a program and data under execution stored in a main storage device 2 and the contents of a display memory 3) The state storage device 1 is composed of a reloadable ROM such as an EEPROM or a flash memory When the power supply switch is turned on, the program executing state is returned to an original state

Abstract: PURPOSE:To contrive the long life and the high performance of a flash EEPROM control circuit and a memory card using it by providing a write verify circuit and an alternate block control circuit. CONSTITUTION:When write is executed from the outside, first of all, last data is erased, and a state where new data is writable is prepared. According to write request, write is executed to a write object block in the flash memory of a main storage part 1 calculated by an address control circuit 4. Then, the written data is read immediately after and compared with the content of a temporarily recorded memory 3 by the write verify circuit and write-verified. At the time of no coincidence, when rewrite number of times arrives at an upper limit value, it is decided that the block is defective. In such a case, by the alternate block control circuit 6, the alternate block of the defective block is provided instantly and write processing is performed. Then, the utilizing term of the device is prolonged and the high performance of the device is contrived.

Abstract: A flash-EPROM cell structure that can be programmed at low drain voltages and low power is disclosed. The new element in the device structure is the incorporation of buried junction at the source side where the high electric field region is established during programming. The cell is programmed by hot-electron injection at the source side and erased by Fowler-Nordheim tunneling at the drain side. Typical programming time of 10 mu s/byte can be accomplished with 3.5 V on the drain junction. The structure can be built with the standard EPROM technology and can offer advantages in low-voltage power supply systems such as portable and notebook computers. >

Abstract: A system detects a pattern of holes in a magnetic medium for determining a characteristic of the tape, such as the type of data contained on the tape. A memory device, such as a FLASH memory, is automatically updated when a predetermined pattern is detected. The updating is performed using a read operation without the need for a host system.

Abstract: A fixed mass storage unit for a data processing system comprising a central processing unit (CPU) exhibits an interface device (8, 9), and a connecting part (13) which can be connected to the CPU (12) is provided into which the interface device of the mass storage unit can be plugged. The mass storage unit can be a fixed-disk storage unit (2), a flash memory storage unit (24) or the like.

Abstract: PURPOSE: To efficiently rewrite firmware by using a flash memory. CONSTITUTION: In order to rewrite the firmware of hardware incorporating software mounted on a microprocessor, the flash memory 26 to store an on-line program and keep its contents even at the time of the disconnection of power supply, an EPROM 25 to store a program for rewriting the flash memory 26, and the transfer device 10 of rewrite data to the flash memory 26 are provided. Besides, a rewrite data storage circuit 23 to store the transfer data of the rewrite data, an OR circuit 21 to switch a reset signal not to rewrite the flash memory and a flash memory rewrite reset signal, and output the generated signal of either a reset generator 30 or the reset generator 30, a circuit 24 to keep a flash memory rewrite reset factor, and a microprocessor bus 27 are provided. COPYRIGHT: (C)1994,JPO&Japio

Abstract: PURPOSE: To realize the stop of memory erasing operation and programming operation by providing a latch, timer and computer memory circuit on a single substrate. CONSTITUTION: A command resistor 38, state control circuit 40, state latch 42 and stop timer 44 are included in a flash memory 10. When the initiation of operation sequence for programming the memory 10 is requested with a command, the command is stored in the commands resistor 38 together with an address and data information required for executing the command. When a set-up erasing command is received with the resistor 38, the byte of the memory 12 is erased. At the same time, a counting operation is executed with a counter within the stop timer 44. When reaching a count value, an erasing pulse is finished to stop erasing.

Abstract: Floating-gate type nonvolatile semiconductor memories (NVSMs) were first introduced and applied by Kahng and Sze in 1967 [1]. The metal-nitride-oxide-silicon (MNOS) structure was first reported by Frohman-Bentchkowsky and Lenzlinger in 1969 [2]. Since then, three families of NVSMs [3–5] have been developed: EPROMs (Erasable and Programmable Read-Only Memories), EEPROMs (Electrically Erasable and Programmable Read-Only Memories), and flash memories (bulk electrically erasable).

Abstract: PURPOSE:To prevent an erroneous erasure at a nonselection element, to shorten the erasure time at a selection element and to reduce an irregularity in an erasure. CONSTITUTION:In a floating gate 22 for a flash memory, the n concentration on the side of a substrate 2 on the side of a drain 40 is low. Even when a drain voltage is applied at a nonselection element, only a small electric field is generated at a tunnel oxide film 14 and it is possible to prevent an erroneous erasure. The n concentration on the side of a source of the floating gate 22 is high. As a result, when a source voltage is applied at a selection element, a large electric field is generated at the tunnel oxide film 14, and an erasure speed becomes fast. In addition, since a diffused ion amount at the floating gate 22 is small, an oxide ridge is suppressed and an erasure irregularity is hard to occur.