TL;DR: The Sun™ Fireplane two-level cache-coherency protocol is described, and its use in the medium and large-sized UltraSPARC-III-based Sun Fire™ servers is described.
Abstract: System interconnect is a key determiner of the cost, performance, and reliability of large cache-coherent, shared-memory multiprocessors. Interconnect implementations have to accommodate ever greater numbers of ever faster processors. This paper describes the Sun™ Fireplane two-level cache-coherency protocol, and its use in the medium and large-sized UltraSPARC-III-based Sun Fire™ servers.
TL;DR: The Sun Fireplane Interconnect, used inside the Sun Microsystems Ultrasparc III generation of servers and workstations, builds on three generations of interconnects, and provides a significant increase in performance and system bandwidth.
Abstract: A computing system's internal interconnect is a key determiner of its cost, performance, and reliability. The Sun Fireplane Interconnect, used inside the Sun Microsystems Ultrasparc III generation of servers and workstations, builds on three generations of interconnects, and provides a significant increase in performance and system bandwidth.
TL;DR: The Sun/Sup TM/ Fireplane SMP interconnect protocol, and the implementation choices the authors made for the mid-sized Sun Fire/sup TM/ 3800-6800 servers are described.
Abstract: Worldwide server revenue is dominated by symmetric multiprocessor (SMP) systems. The architecture and implementation of the interconnect that maintains system-wide cache coherency is critical to the performance and scalability of SMP systems. This paper describes the Sun/sup TM/ Fireplane SMP interconnect protocol, and the implementation choices we made for the mid-sized Sun Fire/sup TM/ 3800-6800 servers.