Field-programmability

Abstract: Power reduction is of growing importance for field-programmable gate arrays (FPGAs). In this paper, we apply programmable supply voltage (Vdd) to reduce FPGA power. We first design FPGA logic fabrics using dual-Vdd levels and show that field-programmable power supply is required to obtain a satisfactory power-versus-performance tradeoff. We further design FPGA interconnect fabrics for fine-grained Vdd programmability with minimal increase of the number of configuration static-random-access-memory cells. With a simple yet practical computer-aided design flow to leverage the field-programmable dual-Vdd logic and interconnect fabrics, we carry out a highly quantitative study using placed and routed benchmark circuits, and delay, power, and area models obtained from detailed circuit designs. Compared to single-Vdd FPGAs with the Vdd level suggested by the International Technology Roadmap for Semiconductors for 100-nm technology, field-programmable dual-Vdd FPGAs reduce the total power by 47.61% and the energy-delay product by 27.36%

Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The exemplary IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. In an exemplary embodiment, some or all of the computational elements are alternately configured to implement two or more functions.

Abstract: The FPGA (Field Programmable Gate Array) strikes a middle ground in cost/power/performance between ASIC (Application Specific Integrated Circuit) and DSP (Digital Signal Processor), while providing field programmability via reconfiguration of internal interconnect and logic functions. However, most current FPGA-based solutions are highly specialized hardware systems designed for narrowly focused dedicated applications. These systems are typically programmed with low-level hardware description languages (HDL) inherited from ASIC design methodologies. The lack of high-level, user-friendly programming models and modular scalable reusable hardware system architectures is the key factor impeding wider adoption of large-scale FPGA-based system. In this thesis, we have demonstrated the practical application of a new generation of high-end reconfigurable computer (HERC) systems that were built with FPGAs as the sole processing element. Through the design and construction of two generations of the Berkeley Emulation Engine (BEE) systems, a high-level, user-friendly software programming model based on synchronous data flow was developed to provide an efficient and productive design methodology for a wide range of high-performance DSP applications and emulation of wireless communications systems. To date, multi-antenna radio astronomy signal processing has provided the largest-scale application of the BEE2 system. We have successfully demonstrated an 800MHz, billion-channel spectrometer using the BEE2 system on a single antenna, as well as a four-antenna 150MHz imaging correlator. Each BEE2 module provided sustained performance up to 1 trillion integer operations per second, and the BEE2 served as the basic building block for larger-scale systems with one to hundreds of modules. In terms of computational throughput per chip, the FPGAs in the BEE2 system outperform a 720MHz (130nm) DSP by a factor of 10 to 34, a 1 GHz (90nm) DSP by a factor of 7 to 25, and the latest Pentium-4 by a factor of 4 to 13. In terms of power efficiency, the XC2VP70 FPGA delivers 72% to 106% more throughput on 16-bit operations compared to DSPs, and more than 1100% more throughput on 4-bit operations. When compared to microprocessors, the FPGA proved over 100 times more power-efficient. Similarly, the compute throughput per unit chip cost of FPGAs is 20% to 307% more than the 1 GHz DSP, and 50% to 505% more than the 3.8GHz Pentium-4 processor. Combining DSP-like ease of programming, ASIC-like computational efficiency, and the scalability of computer clusters, the BEE2 system is becoming a preferred solution for a variety of high-performance digital signal processing applications. With continued evolution of hardware architecture and improvements in alternative programming models, future generations of HERC systems will serve as general-purpose computing platforms for many additional application domains, including scientific computing and computational biology.

Abstract: A study of simulated InP-based RTD/HFET threshold logic gates (TLGs), deployed in an array suited to the implementation of programmable neural network-like architectures, is carried out. A new programmable TLG and an EX-OR TLG are presented. An array of programmable and non-programmable TLGs is studied to demonstrate an application with field programmability and to determine the suitability of the technology for the realisation of these gates in larger scale integrated circuits. The architecture may have the potential for a flexible platform that will allow training and reconfiguration of a cellular artificial neural network (ANN). The functionality of the circuit architecture is investigated and the effects of variations in device-characteristics, and clocked power supply on its operation are considered to assess the potential use of TLG circuits in the context of larger scale implementations.